TY - GEN
T1 - Intel Accelerators Ecosystem
T2 - 51st ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2024
AU - Yuan, Yifan
AU - Wang, Ren
AU - Ranganathan, Narayan
AU - Rao, Nikhil
AU - Kumar, Sanjay
AU - Lantz, Philip
AU - Sanjeepan, Vivekananthan
AU - Cabrera, Jorge
AU - Kwatra, Atul
AU - Sankaran, Rajesh
AU - Jeong, Ipoom
AU - Kim, Nam Sung
N1 - We would like to thank Gary Brown, Mike Ximing Chen, Naveen Lakkakula, Niall McDonell, David Runberg, Tirthendu Sarkar, Abdullah Sevincer, as well as numerous researchers, architects, and designers at Intel who directly worked and/or provided input on exploring related techniques and their design/implementation. Nam Sung Kim s contribution was supported by a grant from PRISM, one of the seven centers in JUMP 2.0, a Semiconductor Research Corporation (SRC) program sponsored by DARPA, and the Intel TSA 2030 program.
PY - 2024
Y1 - 2024
N2 - A growing demand for hyperscale services has compelled hyperscalers to deploy more compute resources at an unprecedented pace, further accelerated by the demise of Dennard scaling. Meanwhile, a considerable portion of the compute resources are consumed to execute common functions present across the hyperscale services, i.e., datacenter taxes. These challenges motivated many to explore specialized accelerators for these functions. Leading such a technology trend, Intel has integrated diverse on-chip accelerators into its recent flagship datacenter CPU products. Furthermore, to support the easy and efficient use of these accelerators for successful deployment in production hyperscale services, Intel has developed a hardware/software ecosystem. In this paper, we first focus on Intel's holistic efforts to build the hardware/software ecosystem, presenting key SoC-level features that facilitate efficient CPU-accelerator interaction, effortless programming and use, and scalable accelerator sharing and virtualization. Next, we delve into the functions, microarchitectures, and software stacks of three new on-chip accelerators: Data Streaming Accelerator (DSA), In-memory Analytics Accelerator (IAA), and Dynamic Load Balancer (DLB). Lastly, we demonstrate that Intel's on-chip accelerators can not only significantly reduce the datacenter taxes but also accelerate data-intensive applications essential for hyperscale services, with little effort to use the accelerators.
AB - A growing demand for hyperscale services has compelled hyperscalers to deploy more compute resources at an unprecedented pace, further accelerated by the demise of Dennard scaling. Meanwhile, a considerable portion of the compute resources are consumed to execute common functions present across the hyperscale services, i.e., datacenter taxes. These challenges motivated many to explore specialized accelerators for these functions. Leading such a technology trend, Intel has integrated diverse on-chip accelerators into its recent flagship datacenter CPU products. Furthermore, to support the easy and efficient use of these accelerators for successful deployment in production hyperscale services, Intel has developed a hardware/software ecosystem. In this paper, we first focus on Intel's holistic efforts to build the hardware/software ecosystem, presenting key SoC-level features that facilitate efficient CPU-accelerator interaction, effortless programming and use, and scalable accelerator sharing and virtualization. Next, we delve into the functions, microarchitectures, and software stacks of three new on-chip accelerators: Data Streaming Accelerator (DSA), In-memory Analytics Accelerator (IAA), and Dynamic Load Balancer (DLB). Lastly, we demonstrate that Intel's on-chip accelerators can not only significantly reduce the datacenter taxes but also accelerate data-intensive applications essential for hyperscale services, with little effort to use the accelerators.
KW - DLB
KW - DSA
KW - IAA
KW - QAT
KW - SIOV
KW - SoC
KW - Xeon
KW - accelerators
KW - datacenter tax
KW - shared virtual memory
UR - http://www.scopus.com/inward/record.url?scp=85201154789&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85201154789&partnerID=8YFLogxK
U2 - 10.1109/ISCA59077.2024.00066
DO - 10.1109/ISCA59077.2024.00066
M3 - Conference contribution
AN - SCOPUS:85201154789
T3 - Proceedings - International Symposium on Computer Architecture
SP - 848
EP - 862
BT - Proceeding - 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture, ISCA 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 June 2024 through 3 July 2024
ER -