@inproceedings{7406e25fec8641fda1ebd8d670528913,
title = "Integrated power supply planning and floorplanning",
abstract = "One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insufficient power supply for certain circuit blocks. In this paper, we present an optimal power supply planning algorithm based on network flow to shorten the current paths from power bumps to local power supply wirings. We have incorporated our algorithm into a floorplanning algorithm for integrated floorplanning and power supply planning. Experimental results are encouraging.",
keywords = "Circuit noise, Design engineering, Noise reduction, Power engineering and energy, Power engineering computing, Power supplies, Routing, Switching circuits, Very large scale integration, Voltage",
author = "Liu, {I. Min} and Chen, {Hung Ming} and Chou, {Tan Li} and A. Aziz and Wong, {D. F.}",
note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",
year = "2001",
doi = "10.1109/ASPDAC.2001.913372",
language = "English (US)",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "589--594",
booktitle = "Proceedings of the ASP-DAC 2001",
address = "United States",
}