Abstract
Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 609-614 |
| Number of pages | 6 |
| Journal | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| DOIs | |
| State | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA Duration: Oct 5 1998 → Oct 7 1998 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering