Integrated partitioning and scheduling for hardware/software co-design

Huiqun Liu, Martin D F Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

Original languageEnglish (US)
Title of host publicationVLSI in Computers and Processors
PublisherIEEE
Pages609-614
Number of pages6
StatePublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: Oct 5 1998Oct 7 1998

Other

OtherProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period10/5/9810/7/98

Fingerprint

Scheduling
Hardware
Application specific integrated circuits
Computer hardware
Program processors
Field programmable gate arrays (FPGA)
Costs
Experiments

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Liu, H., & Wong, M. D. F. (1998). Integrated partitioning and scheduling for hardware/software co-design. In VLSI in Computers and Processors (pp. 609-614). IEEE.

Integrated partitioning and scheduling for hardware/software co-design. / Liu, Huiqun; Wong, Martin D F.

VLSI in Computers and Processors. IEEE, 1998. p. 609-614.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, H & Wong, MDF 1998, Integrated partitioning and scheduling for hardware/software co-design. in VLSI in Computers and Processors. IEEE, pp. 609-614, Proceedings of the 1998 IEEE International Conference on Computer Design, Austin, TX, USA, 10/5/98.
Liu H, Wong MDF. Integrated partitioning and scheduling for hardware/software co-design. In VLSI in Computers and Processors. IEEE. 1998. p. 609-614
Liu, Huiqun ; Wong, Martin D F. / Integrated partitioning and scheduling for hardware/software co-design. VLSI in Computers and Processors. IEEE, 1998. pp. 609-614
@inproceedings{4bdbe95b7bb743978b3f21e76ebcdd58,
title = "Integrated partitioning and scheduling for hardware/software co-design",
abstract = "Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.",
author = "Huiqun Liu and Wong, {Martin D F}",
year = "1998",
language = "English (US)",
pages = "609--614",
booktitle = "VLSI in Computers and Processors",
publisher = "IEEE",

}

TY - GEN

T1 - Integrated partitioning and scheduling for hardware/software co-design

AU - Liu, Huiqun

AU - Wong, Martin D F

PY - 1998

Y1 - 1998

N2 - Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

AB - Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

UR - http://www.scopus.com/inward/record.url?scp=0032303533&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032303533&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0032303533

SP - 609

EP - 614

BT - VLSI in Computers and Processors

PB - IEEE

ER -