Instruction scheduling for low power on dynamically variable voltage processors

Mohammad M. Mansour, Makram M. Mansour, Ibrahim Hajj, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Low power design has become an essential ingredient of modern VLSI design. In this paper, we consider low power design at the circuit and behavioral levels, and in particular, scheduling operations on dynamically variable voltage functional units. Previous attempts did not consider instruction latencies and pipelining effects in scheduling. We propose a timing-constrained and a resource-constrained instruction scheduling algorithm for low power on pipelined functional units considering instruction latencies. Experimental results from scheduling the operations of a digital lattice filter demonstrate the effectiveness of our algorithm.

Original languageEnglish (US)
Title of host publicationICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems
Pages613-618
Number of pages6
DOIs
StatePublished - Dec 1 2000
Event7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon
Duration: Dec 17 2000Dec 20 2000

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Other

Other7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
CountryLebanon
CityJounieh
Period12/17/0012/20/00

Keywords

  • Instruction scheduling
  • List scheduling
  • Variable voltage processors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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