Instruction scheduling for low power on dynamically variable voltage processors

Mohammad M. Mansour; Makram M. Mansour; Ibrahim Hajj; Naresh Shanbhag

doi:10.1109/ICECS.2000.911614

Instruction scheduling for low power on dynamically variable voltage processors

Mohammad M. Mansour, Makram M. Mansour, Ibrahim Hajj, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Low power design has become an essential ingredient of modern VLSI design. In this paper, we consider low power design at the circuit and behavioral levels, and in particular, scheduling operations on dynamically variable voltage functional units. Previous attempts did not consider instruction latencies and pipelining effects in scheduling. We propose a timing-constrained and a resource-constrained instruction scheduling algorithm for low power on pipelined functional units considering instruction latencies. Experimental results from scheduling the operations of a digital lattice filter demonstrate the effectiveness of our algorithm.

Original language	English (US)
Title of host publication	ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems
Pages	613-618
Number of pages	6
DOIs	https://doi.org/10.1109/ICECS.2000.911614
State	Published - 2000
Event	7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon Duration: Dec 17 2000 → Dec 20 2000

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Other

Other	7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
Country/Territory	Lebanon
City	Jounieh
Period	12/17/00 → 12/20/00

Keywords

Instruction scheduling
List scheduling
Variable voltage processors

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/ICECS.2000.911614

Library availability

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Mansour, M. M., Mansour, M. M., Hajj, I., & Shanbhag, N. (2000). Instruction scheduling for low power on dynamically variable voltage processors. In ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems (pp. 613-618). Article 911614 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1). https://doi.org/10.1109/ICECS.2000.911614

Instruction scheduling for low power on dynamically variable voltage processors. / Mansour, Mohammad M.; Mansour, Makram M.; Hajj, Ibrahim et al.
ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems. 2000. p. 613-618 911614 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mansour, MM, Mansour, MM, Hajj, I & Shanbhag, N 2000, Instruction scheduling for low power on dynamically variable voltage processors. in ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems., 911614, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 613-618, 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, 12/17/00. https://doi.org/10.1109/ICECS.2000.911614

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AB - Low power design has become an essential ingredient of modern VLSI design. In this paper, we consider low power design at the circuit and behavioral levels, and in particular, scheduling operations on dynamically variable voltage functional units. Previous attempts did not consider instruction latencies and pipelining effects in scheduling. We propose a timing-constrained and a resource-constrained instruction scheduling algorithm for low power on pipelined functional units considering instruction latencies. Experimental results from scheduling the operations of a digital lattice filter demonstrate the effectiveness of our algorithm.

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Instruction scheduling for low power on dynamically variable voltage processors

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Keywords

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