An integrated circuit for implementing an inner product function is described. Inner Product computers have applications in such areas as high speed image reconstruction, computerized tomography, and signal processing. The circuit to be described computes an inner product of two vectors of 8-bit two's complement integers. Architectural and process design considerations are discussed. The architecture is based on a two's complement quasi-serial multiplier. The chip is fabricated using a depletion-load NMOS Si-gate technology using lambda equals 4 mu m design rules, and occupies an area of 36 mm. Operating times of 80 ns for register-register transfer, 3 mu s for full inner product calculation are achieved, with power dissipation of 80 mW at a supply voltage of 5V.
|Original language||English (US)|
|Number of pages||3|
|State||Published - 1984|
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