Abstract
The inelastic electron tunneling spectroscopy (IETS) was used for studying the traps in ultrathin high-k gate dielectrics. The electrical stress-induced traps in metal-oxide-semiconductor (MOS) structures were also analyzed. The IETS technique identified two different types of trap effects, including carrier trapping and trapping assisted conditions. The results show that the MOS capacitors with thermal silica (SiO 2) as the gate dielectrics had fewer trap-related features and required higher stress voltages to generated the trap related defects.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 5461-5463 |
| Number of pages | 3 |
| Journal | Applied Physics Letters |
| Volume | 83 |
| Issue number | 26 |
| DOIs | |
| State | Published - Dec 29 2003 |
| Externally published | Yes |
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)