Incremental compiler transformations for multiple instruction retry

Shyh‐Kwei ‐K Chen, Neal J. Alewine, W. Kent Fuchs, Wen‐Mei W. Hwu

Research output: Contribution to journalArticle

Abstract

Previous work on compiler‐based multiple instruction retry has utilized a series of compiler transformations, loop protection, node splitting, and loop expansion, to eliminate anti‐dependencies of length ≤ N in the pseudo register, the machine register, and the post‐pass resolver phases of compilation.1 The results have provided a means of rapidly recovering from transient processor failures by rolling back N instructions. This paper presents techniques for improving compilation and run‐time performance in compiler‐based multiple instruction retry. Incremental updating enhances compilation time when new instructions are added to the program. Post‐pass code rescheduling and spill register reassignment algorithms improve the run‐time performance and decrease the code growth across the application programs studied. Branch hazards are shown to be resolvable by simple modifications to the incremental updating schemes during the pseudo register phase and to the spill register reassignment algorithm during the post‐pass phase.

Original languageEnglish (US)
Pages (from-to)1179-1198
Number of pages20
JournalSoftware: Practice and Experience
Volume24
Issue number12
DOIs
StatePublished - Dec 1994

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Keywords

  • Fault‐tolerant computing
  • Instruction retry
  • Rollback recovery

ASJC Scopus subject areas

  • Software

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