InAs Planar Nanowire Gate-All-Around MOSFETs on GaAs Substrates by Selective Lateral Epitaxy

Chen Zhang, Wonsik Choi, Parsian K. Mohseni, Xiuling Li

Research output: Contribution to journalArticlepeer-review

Abstract

High indium content III-V materials are one of the most promising candidates for beyond Si CMOS technologies. We present InAs planar nanowire (NW) MOSFETs grown directly on a semi-insulating GaAs (100) substrate by the selective lateral epitaxy (SLE) method via the metal-seeded planar vapor-liquid-solid mechanism. Despite a \sim 7 % lattice mismatch, in-plane and self-aligned single-crystal InAs NWs are grown epitaxially on GaAs. Such heterogeneous SLE provides a potential solution for the integration of different channel materials on one substrate. Gate-all-around MOSFET devices are fabricated by releasing the NW channel from the substrate through a combination of digital etching and selective etching processes. The device with a NW width of 30 nm and gate length of 350 nm shows an IONOFF ratio of 104} and a peak transconductance of 220 mS/mm at V-{\mathrm {ds}} = 0.5 V.

Original languageEnglish (US)
Article number7101804
Pages (from-to)663-665
Number of pages3
JournalIEEE Electron Device Letters
Volume36
Issue number7
DOIs
StatePublished - Jul 1 2015

Keywords

  • III-V MOSFETs
  • InAs
  • Nanowire
  • Selective Lateral Epitaxy
  • VLS Growth

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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