Improving trace cache effectiveness with branch promotion and trace packing

Sanjay Jeram Patel, Marius Evers, Yale N. Patt

Research output: Contribution to journalConference article


The increasing widths of superscalar processors are placing greater demands upon the fetch mechanism. The trace cache meets these demands by placing logically contiguous instructions in physically contiguous storage. As a result, the trace cache delivers instructions at a high rate by supplying multiple fetch blocks each cycle. In this paper, we examine two techniques to improve the number of instructions delivered each cycle by the trace cache. The first technique, branch promotion, dynamically converts strongly biased branches into branches with static predictions. Because these promoted branches require no dynamic prediction, the branch predictor suffers less from the negative effects of interference. Branch promotion unlocks the potential of the second technique: trace packing. With trace packing, trace segments are packed with as many instructions as will fit, without regard to naturally occurring fetch block boundaries. With both techniques, the effective fetch rate of the trace cache jumps up 17% over a trace cache which implements neither. On a machine where the execution engine has a very aggressive memory disambiguator, the performance of a machine using branch promotion and trace packing is on average 11% higher than a machine using neither technique.

Original languageEnglish (US)
Pages (from-to)262-271
Number of pages10
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - Jan 1 1998
Externally publishedYes
EventProceedings of the 1998 25th Annual International Symposium on Computer Architecture - Barcelona, Spain
Duration: Jun 27 1998Jul 1 1998

ASJC Scopus subject areas

  • Hardware and Architecture

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