Improving throughput of power-constrained many-core processors based on unreliable devices

It has been reported that carbon nanotube (CNT) devices are faster and consume less power than CMOS devices. However, current CNT devices exhibit a higher defect rate than CMOS devices. To reduce the defect rate of CNT devices, a device-level redundancy technique can be adopted. However, more device-level redundancy in turn increases area, delay, and power consumption of integrated circuits (ICs). In this article, the authors propose to use slightly less device-level redundancy than required for all processor cores to be defect-free for a yield target, which makes cores smaller, faster, and more power efficient. Although some cores can be defective with less device-level redundancy, many-core processors can tolerate some defective cores by design. Under the same power and yield constraints, the authors demonstrate that a CNT processor with less device-level redundancy can provide 1.75 times higher throughput despite also being nearly 2 times smaller than a CNT processor that has more device-level redundancy and that also makes all cores defect free.