Improving throughput of power-constrained GPUs using dynamic voltage/frequency and core scaling

Jungseob Lee, Vijay Sathisha, Michael Schulte, Katherine Compton, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

State-of-the-art graphic processing units (GPUs) can offer very high computational throughput for highly parallel applications using hundreds of integrated cores. In general, the peak throughput of a GPU is proportional to the product of the number of cores and their frequency. However, the product is often limited by a power constraint. Although the throughput can be increased with more cores for some applications, it cannot for others because parallelism of applications and/or bandwidth of on-chip interconnects/caches and off-chip memory are limited. In this paper, first, we demonstrate that adjusting the number of operating cores and the voltage/frequency of cores and/or on-chip interconnects/caches for different applications can improve the throughput of GPUs under a power constraint. Second, we show that dynamically scaling the number of operating cores and the voltages/frequencies of both cores and on-chip interconnects/caches at runtime can improve the throughput of application even further. Our experimental results show that a GPU adopting our runtime dynamic voltage/frequency and core scaling technique can provide up to 38% (and nearly 20% on average) higher throughput than the baseline GPU under the same power constraint.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011
Pages111-120
Number of pages10
DOIs
StatePublished - Dec 1 2011
Externally publishedYes
Event20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011 - Galveston, TX, United States
Duration: Oct 10 2011Oct 14 2011

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011
CountryUnited States
CityGalveston, TX
Period10/10/1110/14/11

Keywords

  • Dynamic voltage, frequency, and core scaling
  • GPU
  • Power constraint
  • Throughput

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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