Improving the data cache performance of multiprocessor operating systems

Chun Xia, Josep Torrellas

Research output: Contribution to conferencePaper

Abstract

Bus-based shared-memory multiprocessors with coherent caches have recently become very popular. To achieve high performance, these systems rely on increasingly sophisticated cache hierarchies. However, while these machines often run loads with substantial operating system activity, performance measurements have consistently indicated that the operating system uses the data cache hierarchy poorly. In this paper, we address the issue of how to eliminate most of the data cache misses in a multiprocessor operating system while still using off-the-shelf processors. We use a performance monitor to examine traces of a 4-processor machine running four system-intensive loads under UNIX. Based on our observations, we propose hardware and software support that targets block operations, coherence activity, and cache conflicts. For block operations, simple cache bypassing or prefetching schemes are undesirable. Instead, it is best to use a DMA-like scheme that pipelines the data transfer in the bus without involving the processor. Coherence misses are handled with data privatization and relocation, and the use of updates for a small core of shared variables. Finally, the remaining miss hot spots are handled with data prefetching. Overall, our simulations show that all these optimizations combined eliminate or hide 75% of the operating system data misses in 32-Kbyte primary caches. Furthermore, they speed up the operating system by 19%.

Original languageEnglish (US)
Pages85-94
Number of pages10
StatePublished - Jan 1 1996
EventProceedings of the 1996 2nd International Symposium on High-Performance Computer Architecture, HPCA - San Jose, CA, USA
Duration: Feb 3 1996Feb 7 1996

Other

OtherProceedings of the 1996 2nd International Symposium on High-Performance Computer Architecture, HPCA
CitySan Jose, CA, USA
Period2/3/962/7/96

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Xia, C., & Torrellas, J. (1996). Improving the data cache performance of multiprocessor operating systems. 85-94. Paper presented at Proceedings of the 1996 2nd International Symposium on High-Performance Computer Architecture, HPCA, San Jose, CA, USA, .