Improving the accuracy vs. speed tradeoff for simulating shared-memory multiprocessors with ILP processors

Murthy Durbhakula, Vijay S. Pai, Sarita V Adve

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not exploit common instruction-level parallelism (ILP) features, consequently exhibiting large errors when used to model current systems. A few newer simulators model current ILP processors in detail, but we find them to be about ten times slower. We propose a new simulation technique, based on a novel adaptation of direct execution, that alleviates this accuracy vs. speed tradeoff. We compare the speed and accuracy of our new simulator, DirectRSIM, with three other simulators - RSIM (a detailed simulator for multiprocessors with ILP processors) and two representative simple-processor based simulators. Compared to RSIM, on average, DirectRSIM is 3.6 times faster and exhibits a relative error of only 1.3% in total execution time. Compared to the simple-processor based simulators, DirectRSIM is far superior in accuracy, and yet is only 2.7 times slower.

Original languageEnglish (US)
Title of host publicationIEEE High-Performance Computer Architecture Symposium Proceedings
PublisherIEEE Comp Soc
Pages23-32
Number of pages10
StatePublished - 1999
Externally publishedYes
EventProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA - Orlando, FL, USA
Duration: Jan 9 1999Jan 13 1999

Other

OtherProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA
CityOrlando, FL, USA
Period1/9/991/13/99

ASJC Scopus subject areas

  • Engineering(all)

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    Durbhakula, M., Pai, V. S., & Adve, S. V. (1999). Improving the accuracy vs. speed tradeoff for simulating shared-memory multiprocessors with ILP processors. In IEEE High-Performance Computer Architecture Symposium Proceedings (pp. 23-32). IEEE Comp Soc.