Improving quasi-dynamic schedules through region slip

F. Spadini, B. Fahs, S. Patel, S. S. Lumetta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Modern processors perform dynamic scheduling to achieve better utilization of execution resources. A schedule created at run-time is often better than one created at compile-time as it can dynamically adapt to specific events encountered at execution-time. In this paper, we examine some fundamental impediments to effective static scheduling. More specifically, we examine the question of why schedules generated quasi-dynamically by a low-level runtime optimizer and executed on a statically scheduled machine perform worse than using a dynamically-scheduled approach. We observe that such schedules suffer because of region boundaries and a skewed distribution of parallelism towards the beginning of a region. To overcome these limitations, we investigate a new concept, region slip, in which the schedules of different statically-scheduled regions can be interleaved in the processor issue queue to reduce the region boundary effects that cause empty issue slots.

Original languageEnglish (US)
Title of host publicationInternational Symposium on Code Generation and Optimization, CGO 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages149-158
Number of pages10
ISBN (Electronic)076951913X, 9780769519135
DOIs
StatePublished - 2003
EventInternational Symposium on Code Generation and Optimization, CGO 2003 - San Francisco, United States
Duration: Mar 23 2003Mar 26 2003

Publication series

NameInternational Symposium on Code Generation and Optimization, CGO 2003

Other

OtherInternational Symposium on Code Generation and Optimization, CGO 2003
Country/TerritoryUnited States
CitySan Francisco
Period3/23/033/26/03

Keywords

  • Costs
  • Dynamic scheduling
  • Fuels
  • Hardware
  • High performance computing
  • Impedance
  • Microprocessors
  • Parallel processing
  • Processor scheduling
  • Runtime

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing

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