Improving memory scheduling via processor-side load criticality information

Saugata Ghose, Hyodong Lee, José F. Martínez

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We hypothesize that performing processor-side analysis of load instructions, and providing this pre-digested information to memory schedulers judiciously, can increase the sophistication of memory decisions while maintaining a lean memory controller that can take scheduling actions quickly. This is increasingly important as DRAM frequencies continue to increase relative to processor speed. In this paper we propose one such mechanism, pairing up a processor-side load criticality predictor with a lean memory controller that prioritizes load requests based on ranking information supplied from the processor side. Using a sophisticated multi-core simulator that includes a detailed quad-channel DDR3 DRAM model, we demonstrate that this mechanism can improve performance significantly on a CMP, with minimal overhead and virtually no changes to the processor itself. We show that our design compares favorably to several state-of-the-art schedulers.

Original languageEnglish (US)
Title of host publicationISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings
Pages84-95
Number of pages12
DOIs
StatePublished - 2013
Externally publishedYes
Event40th Annual International Symposium on Computer Architecture, ISCA 2013 - Tel-Aviv, Israel
Duration: Jun 23 2013Jun 27 2013

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other40th Annual International Symposium on Computer Architecture, ISCA 2013
CountryIsrael
CityTel-Aviv
Period6/23/136/27/13

ASJC Scopus subject areas

  • Hardware and Architecture

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