Improved Si₃N₄/Si/GaAs metal-insulator-semiconductor interfaces by in situ anneal of the as-deposited Si

Si interlayers in GaAs metal-insulator-semiconductor structures are essential for interfaces with device quality. The incompatible growth temperature of Si on GaAs, however, presents a dilemma between the crystallinity of Si and the stoichiometry of GaAs. We circumvented this dilemma by a new approach: a high-temperature in situ anneal following the low-temperature Si deposition. The idea is that the GaAs surface covered with a few monolayers of Si can stand a much higher temperature, and the crystal quality of the Si is resumed during the high-temperature anneal. The surface morphology of the as-deposited and the in situ annealed Si was examined with a scanning tunneling microscope, the results of which confirmed high crystal quality of the Si layer and full coverage of the GaAs surface. With in situ anneal, interface trap densities of high 10¹⁰ eV^-1 cm^-2 were routinely obtained in Si₃N₄/Si/GaAs metal-insulator-semiconductor capacitors, as determined with conductance measurements.