Improved latency insertion method for simulation of large networks with low latency

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, a block processing method is introduced to increase the speed of the latency insertion method while maintaining stability. By partitioning a large network into blocks, the simulation speed increases and memory usage is reduced significantly.

Original languageEnglish (US)
Title of host publicationElectrical Performance of Electronic Packaging, EPEP 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages37-40
Number of pages4
ISBN (Electronic)0780374517
DOIs
StatePublished - Jan 1 2002
Event11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 - Monterey, United States
Duration: Oct 21 2002Oct 23 2002

Publication series

NameIEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume2002-January

Other

Other11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
CountryUnited States
CityMonterey
Period10/21/0210/23/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Gao, R., & Schutt-Aine, J. E. (2002). Improved latency insertion method for simulation of large networks with low latency. In Electrical Performance of Electronic Packaging, EPEP 2002 (pp. 37-40). [1057878] (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEP.2002.1057878