Improved latency insertion method for simulation of large networks with low latency

R. Gao; J. E. Schutt-Ainé

doi:10.1109/EPEP.2002.1057878

Improved latency insertion method for simulation of large networks with low latency

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this work, a block processing method is introduced to increase the speed of the latency insertion method while maintaining stability. By partitioning a large network into blocks, the simulation speed increases and memory usage is reduced significantly.

Original language	English (US)
Title of host publication	Electrical Performance of Electronic Packaging, EPEP 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	37-40
Number of pages	4
ISBN (Electronic)	0780374517
DOIs	https://doi.org/10.1109/EPEP.2002.1057878
State	Published - 2002
Event	11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 - Monterey, United States Duration: Oct 21 2002 → Oct 23 2002

Publication series

Name	IEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume	2002-January

Other

Other	11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Country/Territory	United States
City	Monterey
Period	10/21/02 → 10/23/02

ASJC Scopus subject areas

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

Online availability

10.1109/EPEP.2002.1057878

Library availability

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Cite this

Gao, R., & Schutt-Ainé, J. E. (2002). Improved latency insertion method for simulation of large networks with low latency. In Electrical Performance of Electronic Packaging, EPEP 2002 (pp. 37-40). [1057878] (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEP.2002.1057878

Improved latency insertion method for simulation of large networks with low latency. / Gao, R.; Schutt-Ainé, J. E.
Electrical Performance of Electronic Packaging, EPEP 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 37-40 1057878 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Gao, R & Schutt-Ainé, JE 2002, Improved latency insertion method for simulation of large networks with low latency. in Electrical Performance of Electronic Packaging, EPEP 2002., 1057878, IEEE Topical Meeting on Electrical Performance of Electronic Packaging, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 37-40, 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002, Monterey, United States, 10/21/02. https://doi.org/10.1109/EPEP.2002.1057878

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Improved latency insertion method for simulation of large networks with low latency

Abstract

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