@inproceedings{fd4bbf84987c49c493486c0e50177002,
title = "Improved GGSCR layout for overshoot reduction",
abstract = "A new layout of the GGSCR ESD protection device is proposed for transient voltage overshoot reduction. The superior performance of the modified layout is verified in 65nm CMOS technology. Even with the modified layout, key layout spacings, such as the well-tap spacing and the anode to cathode spacing, affect the overshoot voltage. An n-well triggered version of the GGSCR is compared with the usual p-well triggered device and is shown to have larger overshoot. Finally, the susceptibility of the trigger GGNMOS to undergo early failure is investigated.",
keywords = "ESD, GGSCR, overshoot",
author = "Zaichen Chen and Robert Mertens and Collin Reiman and Elyse Rosenbaum",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Reliability Physics Symposium, IRPS 2015 ; Conference date: 19-04-2015 Through 23-04-2015",
year = "2015",
month = may,
day = "26",
doi = "10.1109/IRPS.2015.7112720",
language = "English (US)",
series = "IEEE International Reliability Physics Symposium Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "3F21--3F28",
booktitle = "2015 IEEE International Reliability Physics Symposium, IRPS 2015",
address = "United States",
}