Improved GGSCR layout for overshoot reduction

Zaichen Chen, Robert Mertens, Collin Reiman, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A new layout of the GGSCR ESD protection device is proposed for transient voltage overshoot reduction. The superior performance of the modified layout is verified in 65nm CMOS technology. Even with the modified layout, key layout spacings, such as the well-tap spacing and the anode to cathode spacing, affect the overshoot voltage. An n-well triggered version of the GGSCR is compared with the usual p-well triggered device and is shown to have larger overshoot. Finally, the susceptibility of the trigger GGNMOS to undergo early failure is investigated.

Original languageEnglish (US)
Title of host publication2015 IEEE International Reliability Physics Symposium, IRPS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467373623
StatePublished - May 26 2015
EventIEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States
Duration: Apr 19 2015Apr 23 2015

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026


OtherIEEE International Reliability Physics Symposium, IRPS 2015
Country/TerritoryUnited States


  • ESD
  • overshoot

ASJC Scopus subject areas

  • General Engineering


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