Implicitly parallel programming models for thousand-core microprocessors

Wen Mei Hwu; Shane Ryoo; Sain Zee Ueng; John H. Keim; Isaac Gelado; Sam S. Stone; Robert E. Kidd; Sara S. Baghsorkhi; Aqeel A. Mahesri; Stephanie C. Tsao; Nacho Navarro; Steve S. Lumetta; Matthew I. Frank; Sanjay J. Patel

doi:10.1109/DAC.2007.375265

Implicitly parallel programming models for thousand-core microprocessors

Wen Mei Hwu, Shane Ryoo, Sain Zee Ueng, John H. Keim, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel A. Mahesri, Stephanie C. Tsao, Nacho Navarro, Steve S. Lumetta, Matthew I. Frank, Sanjay J. Patel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithmlevel parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.

Original language	English (US)
Title of host publication	2007 44th ACM/IEEE Design Automation Conference, DAC'07
Pages	754-759
Number of pages	6
DOIs	https://doi.org/10.1109/DAC.2007.375265
State	Published - 2007
Event	2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States Duration: Jun 4 2007 → Jun 8 2007

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Other

Other	2007 44th ACM/IEEE Design Automation Conference, DAC'07
Country/Territory	United States
City	San Diego, CA
Period	6/4/07 → 6/8/07

Keywords

Parallel programming

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering

Online availability

10.1109/DAC.2007.375265

Library availability

Discover UIUC Full Text

Cite this

Hwu, W. M., Ryoo, S., Ueng, S. Z., Keim, J. H., Gelado, I., Stone, S. S., Kidd, R. E., Baghsorkhi, S. S., Mahesri, A. A., Tsao, S. C., Navarro, N., Lumetta, S. S., Frank, M. I., & Patel, S. J. (2007). Implicitly parallel programming models for thousand-core microprocessors. In 2007 44th ACM/IEEE Design Automation Conference, DAC'07 (pp. 754-759). Article 4261284 (Proceedings - Design Automation Conference). https://doi.org/10.1109/DAC.2007.375265

Hwu, WM, Ryoo, S, Ueng, SZ, Keim, JH, Gelado, I, Stone, SS, Kidd, RE, Baghsorkhi, SS, Mahesri, AA, Tsao, SC, Navarro, N, Lumetta, SS, Frank, MI & Patel, SJ 2007, Implicitly parallel programming models for thousand-core microprocessors. in 2007 44th ACM/IEEE Design Automation Conference, DAC'07., 4261284, Proceedings - Design Automation Conference, pp. 754-759, 2007 44th ACM/IEEE Design Automation Conference, DAC'07, San Diego, CA, United States, 6/4/07. https://doi.org/10.1109/DAC.2007.375265

@inproceedings{30c1d54e8bd44b928dca46a49ac46762,

title = "Implicitly parallel programming models for thousand-core microprocessors",

abstract = "This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithmlevel parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.",

keywords = "Parallel programming",

author = "Hwu, {Wen Mei} and Shane Ryoo and Ueng, {Sain Zee} and Keim, {John H.} and Isaac Gelado and Stone, {Sam S.} and Kidd, {Robert E.} and Baghsorkhi, {Sara S.} and Mahesri, {Aqeel A.} and Tsao, {Stephanie C.} and Nacho Navarro and Lumetta, {Steve S.} and Frank, {Matthew I.} and Patel, {Sanjay J.}",

year = "2007",

doi = "10.1109/DAC.2007.375265",

language = "English (US)",

isbn = "1595936270",

series = "Proceedings - Design Automation Conference",

pages = "754--759",

booktitle = "2007 44th ACM/IEEE Design Automation Conference, DAC'07",

note = "2007 44th ACM/IEEE Design Automation Conference, DAC'07 ; Conference date: 04-06-2007 Through 08-06-2007",

}

TY - GEN

T1 - Implicitly parallel programming models for thousand-core microprocessors

AU - Hwu, Wen Mei

AU - Ryoo, Shane

AU - Ueng, Sain Zee

AU - Keim, John H.

AU - Gelado, Isaac

AU - Stone, Sam S.

AU - Kidd, Robert E.

AU - Baghsorkhi, Sara S.

AU - Mahesri, Aqeel A.

AU - Tsao, Stephanie C.

AU - Navarro, Nacho

AU - Lumetta, Steve S.

AU - Frank, Matthew I.

AU - Patel, Sanjay J.

PY - 2007

Y1 - 2007

N2 - This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithmlevel parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.

AB - This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithmlevel parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.

KW - Parallel programming

UR - http://www.scopus.com/inward/record.url?scp=34547288235&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547288235&partnerID=8YFLogxK

U2 - 10.1109/DAC.2007.375265

DO - 10.1109/DAC.2007.375265

M3 - Conference contribution

AN - SCOPUS:34547288235

SN - 1595936270

SN - 9781595936271

T3 - Proceedings - Design Automation Conference

SP - 754

EP - 759

BT - 2007 44th ACM/IEEE Design Automation Conference, DAC'07

T2 - 2007 44th ACM/IEEE Design Automation Conference, DAC'07

Y2 - 4 June 2007 through 8 June 2007

ER -

Implicitly parallel programming models for thousand-core microprocessors

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Online availability

Library availability

Related links

Fingerprint

Cite this