Implementation of a parallel prolog interpreter on multiprocessors

Laxmikant V. Kalé, Balkrishna Ramkumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We describe the implementation of the Reduce-OR process model for the parallel execution of logic programs in an interpreter for parallel Prolog. The interpreter supports full OR and independent AND parallelism in logic programs on both shared and nonshared memory machines. The process model has been implemented on top of a run time support system called the Chare Kernel The Chare Kernel makes it possible to keep the interpreter machine independent by assuming responsibility for dynamic load balancing, scheduling, memory and task queue management. The interpreter currently runs on the Sequent Balance, the Alliant FX/8, the Encore Multimax and the Intel iPSC/2 hypercube. This implementation provides valuable information for the design and development of a compiler for the Reduce- OR process model.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Parallel Processing Symposium, IPPS 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages543-548
Number of pages6
ISBN (Electronic)0818691670, 9780818691676
DOIs
StatePublished - 1991
Event5th International Parallel Processing Symposium, IPPS 1991 - Anaheim, United States
Duration: Apr 30 1991May 2 1991

Publication series

NameProceedings - 5th International Parallel Processing Symposium, IPPS 1991

Conference

Conference5th International Parallel Processing Symposium, IPPS 1991
Country/TerritoryUnited States
CityAnaheim
Period4/30/915/2/91

ASJC Scopus subject areas

  • Computational Mathematics
  • Hardware and Architecture
  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications

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