The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.