IMPACT: An architectural framework for multiple-instruction-issue processors

Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-Mei W Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherPubl by IEEE
Pages266-275
Number of pages10
ISBN (Print)0897913949
StatePublished - May 1 1991
EventProceedings of the 18th International Symposium on Computer Architecture - Toronto, Ont, Can
Duration: May 27 1991May 30 1991

Publication series

NameConference Proceedings - Annual Symposium on Computer Architecture
ISSN (Print)0149-7111

Other

OtherProceedings of the 18th International Symposium on Computer Architecture
CityToronto, Ont, Can
Period5/27/915/30/91

Fingerprint

Architectural design
Experiments
Scheduling
Data storage equipment

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chang, P. P., Mahlke, S. A., Chen, W. Y., Warter, N. J., & Hwu, W-M. W. (1991). IMPACT: An architectural framework for multiple-instruction-issue processors. In Conference Proceedings - Annual Symposium on Computer Architecture (pp. 266-275). (Conference Proceedings - Annual Symposium on Computer Architecture). Publ by IEEE.

IMPACT : An architectural framework for multiple-instruction-issue processors. / Chang, Pohua P.; Mahlke, Scott A.; Chen, William Y.; Warter, Nancy J.; Hwu, Wen-Mei W.

Conference Proceedings - Annual Symposium on Computer Architecture. Publ by IEEE, 1991. p. 266-275 (Conference Proceedings - Annual Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chang, PP, Mahlke, SA, Chen, WY, Warter, NJ & Hwu, W-MW 1991, IMPACT: An architectural framework for multiple-instruction-issue processors. in Conference Proceedings - Annual Symposium on Computer Architecture. Conference Proceedings - Annual Symposium on Computer Architecture, Publ by IEEE, pp. 266-275, Proceedings of the 18th International Symposium on Computer Architecture, Toronto, Ont, Can, 5/27/91.
Chang PP, Mahlke SA, Chen WY, Warter NJ, Hwu W-MW. IMPACT: An architectural framework for multiple-instruction-issue processors. In Conference Proceedings - Annual Symposium on Computer Architecture. Publ by IEEE. 1991. p. 266-275. (Conference Proceedings - Annual Symposium on Computer Architecture).
Chang, Pohua P. ; Mahlke, Scott A. ; Chen, William Y. ; Warter, Nancy J. ; Hwu, Wen-Mei W. / IMPACT : An architectural framework for multiple-instruction-issue processors. Conference Proceedings - Annual Symposium on Computer Architecture. Publ by IEEE, 1991. pp. 266-275 (Conference Proceedings - Annual Symposium on Computer Architecture).
@inproceedings{10b71a3c415f474ba2a10dfe15fcdcb6,
title = "IMPACT: An architectural framework for multiple-instruction-issue processors",
abstract = "The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.",
author = "Chang, {Pohua P.} and Mahlke, {Scott A.} and Chen, {William Y.} and Warter, {Nancy J.} and Hwu, {Wen-Mei W}",
year = "1991",
month = "5",
day = "1",
language = "English (US)",
isbn = "0897913949",
series = "Conference Proceedings - Annual Symposium on Computer Architecture",
publisher = "Publ by IEEE",
pages = "266--275",
booktitle = "Conference Proceedings - Annual Symposium on Computer Architecture",

}

TY - GEN

T1 - IMPACT

T2 - An architectural framework for multiple-instruction-issue processors

AU - Chang, Pohua P.

AU - Mahlke, Scott A.

AU - Chen, William Y.

AU - Warter, Nancy J.

AU - Hwu, Wen-Mei W

PY - 1991/5/1

Y1 - 1991/5/1

N2 - The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.

AB - The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.

UR - http://www.scopus.com/inward/record.url?scp=0026157612&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026157612&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026157612

SN - 0897913949

T3 - Conference Proceedings - Annual Symposium on Computer Architecture

SP - 266

EP - 275

BT - Conference Proceedings - Annual Symposium on Computer Architecture

PB - Publ by IEEE

ER -