Abstract
The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.
| Original language | English (US) |
|---|---|
| Title of host publication | Conference Proceedings - Annual Symposium on Computer Architecture |
| Publisher | Publ by IEEE |
| Pages | 266-275 |
| Number of pages | 10 |
| ISBN (Print) | 0897913949 |
| State | Published - May 1 1991 |
| Event | Proceedings of the 18th International Symposium on Computer Architecture - Toronto, Ont, Can Duration: May 27 1991 → May 30 1991 |
Publication series
| Name | Conference Proceedings - Annual Symposium on Computer Architecture |
|---|---|
| ISSN (Print) | 0149-7111 |
Other
| Other | Proceedings of the 18th International Symposium on Computer Architecture |
|---|---|
| City | Toronto, Ont, Can |
| Period | 5/27/91 → 5/30/91 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
IMPACT : An architectural framework for multiple-instruction-issue processors. / Chang, Pohua P.; Mahlke, Scott A.; Chen, William Y.; Warter, Nancy J.; Hwu, Wen-Mei W.
Conference Proceedings - Annual Symposium on Computer Architecture. Publ by IEEE, 1991. p. 266-275 (Conference Proceedings - Annual Symposium on Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - IMPACT
T2 - An architectural framework for multiple-instruction-issue processors
AU - Chang, Pohua P.
AU - Mahlke, Scott A.
AU - Chen, William Y.
AU - Warter, Nancy J.
AU - Hwu, Wen-Mei W
PY - 1991/5/1
Y1 - 1991/5/1
N2 - The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.
AB - The optimization capabilities of the IMPACT-I C compiler are summarized. Using this compiler, the authors ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The processors achieved solid speedup over high-performance single-instruction-issue processors. The authors also ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. On the basis of the experimental results, they propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.
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M3 - Conference contribution
AN - SCOPUS:0026157612
SN - 0897913949
T3 - Conference Proceedings - Annual Symposium on Computer Architecture
SP - 266
EP - 275
BT - Conference Proceedings - Annual Symposium on Computer Architecture
PB - Publ by IEEE
ER -