ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

Yi Kan Cheng, Prasun Raha, Chin Chi Teng, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalArticle

Abstract

In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

Original languageEnglish (US)
Pages (from-to)668-681
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume17
Issue number8
DOIs
StatePublished - Dec 1 1998

Fingerprint

VLSI circuits
Simulators
Packaging
Specifications
Temperature
Networks (circuits)
Experiments

Keywords

  • Cmos integrated circuits
  • Electrothermal effects
  • Integrated circuit reliability
  • Temperature
  • Timing

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

ILLIADS-T : An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. / Cheng, Yi Kan; Raha, Prasun; Teng, Chin Chi; Rosenbaum, Elyse; Kang, Sung Mo.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 8, 01.12.1998, p. 668-681.

Research output: Contribution to journalArticle

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