ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

Yi Kan Cheng; Prasun Raha; Chin Chi Teng; Elyse Rosenbaum; Sung Mo Kang

doi:10.1109/43.712099

ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

Yi Kan Cheng, Prasun Raha, Chin Chi Teng, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

Original language	English (US)
Pages (from-to)	668-681
Number of pages	14
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	17
Issue number	8
DOIs	https://doi.org/10.1109/43.712099
State	Published - 1998

Keywords

Cmos integrated circuits
Electrothermal effects
Integrated circuit reliability
Temperature
Timing

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Online availability

10.1109/43.712099

Library availability

Discover UIUC Full Text

Cite this

@article{7c0238b30a5f4fdf9165f641c48f3dd7,

title = "ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips",

abstract = "In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.",

keywords = "Cmos integrated circuits, Electrothermal effects, Integrated circuit reliability, Temperature, Timing",

author = "Cheng, {Yi Kan} and Prasun Raha and Teng, {Chin Chi} and Elyse Rosenbaum and Kang, {Sung Mo}",

note = "Funding Information: Manuscript received May 8, 1997; revised April 3, 1998. This work was supported in part by research grants from the Semiconductor Research Corporation (SRC95-DP-109), the Joint Services Electronics Program (N00014-96-1-0129), and the Air Force Rome Laboratory (F30602-94-1-0006). This paper was recommended by Associate Editor K. Mayaram.",

year = "1998",

doi = "10.1109/43.712099",

language = "English (US)",

volume = "17",

pages = "668--681",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - ILLIADS-T

T2 - An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

AU - Cheng, Yi Kan

AU - Raha, Prasun

AU - Teng, Chin Chi

AU - Rosenbaum, Elyse

AU - Kang, Sung Mo

N1 - Funding Information: Manuscript received May 8, 1997; revised April 3, 1998. This work was supported in part by research grants from the Semiconductor Research Corporation (SRC95-DP-109), the Joint Services Electronics Program (N00014-96-1-0129), and the Air Force Rome Laboratory (F30602-94-1-0006). This paper was recommended by Associate Editor K. Mayaram.

PY - 1998

Y1 - 1998

N2 - In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

AB - In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

KW - Cmos integrated circuits

KW - Electrothermal effects

KW - Integrated circuit reliability

KW - Temperature

KW - Timing

UR - http://www.scopus.com/inward/record.url?scp=0032139246&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032139246&partnerID=8YFLogxK

U2 - 10.1109/43.712099

DO - 10.1109/43.712099

M3 - Article

AN - SCOPUS:0032139246

SN - 0278-0070

VL - 17

SP - 668

EP - 681

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 8

ER -

ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

Abstract

Keywords

ASJC Scopus subject areas

Online availability

Library availability

Related links

Fingerprint

Cite this