III-V nanowire transistors for low-power logic applications: A review and outlook

Chen Zhang, Xiuling Li

Research output: Contribution to journalArticle

Abstract

III-V semiconductors, especially InAs, have much higher electron mobilities than Si and have been considered as promising candidates for n-channel materials for post-Si low-power CMOS logic applications. Combined with the inherent 3-D structure that enables the gate-all-around (GAA) geometry for superb gate electrostatic control, III-V nanowire (NW) MOS-FETs are well positioned to extend the scaling beyond Si. This paper attempts to provide a review of the growth and fabrication approaches (both bottom-up and top-down), and the state-of-the-art device performance of III-V NW GAA MOSFETs, as well as an outlook of their scaling potential.

Original languageEnglish (US)
Article number7160680
Pages (from-to)223-234
Number of pages12
JournalIEEE Transactions on Electron Devices
Volume63
Issue number1
DOIs
StatePublished - Jan 1 2016

Fingerprint

Nanowires
Transistors
Electron mobility
Field effect transistors
Electrostatics
Fabrication
Geometry
III-V semiconductors
indium arsenide

Keywords

  • Gate-all-around (GAA)
  • III-V
  • MOSFET
  • Nanowire (NW)
  • Scaling

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

III-V nanowire transistors for low-power logic applications : A review and outlook. / Zhang, Chen; Li, Xiuling.

In: IEEE Transactions on Electron Devices, Vol. 63, No. 1, 7160680, 01.01.2016, p. 223-234.

Research output: Contribution to journalArticle

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