III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications

Yi Song, Chen Zhang, Ryan Dowdy, Kelson Chabak, Parsian K. Mohseni, Wonsik Choi, Xiuling Li

Research output: Contribution to journalArticle

Abstract

III-V junctionless gate-all-around (GAA) nanowire MOSFETs (NWFETs) are experimentally demonstrated for the first time. Source/drain resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition instead of implantation. The fabricated short channel (L g=80nm GaAs GAA NWFETs with extremely scaled NW width W NW=9 nm exhibit excellent gm linearity at biases as low as 300 mV, characterized by the high third intercept point (2.6 dbm). The high linearity is insensitive to the bias conditions, which is favorable for low power applications.

Original languageEnglish (US)
Article number6705581
Pages (from-to)324-326
Number of pages3
JournalIEEE Electron Device Letters
Volume35
Issue number3
DOIs
StatePublished - Mar 1 2014

Keywords

  • GaAs MOSFET
  • gate-all-around (GAA)
  • implantation-free junctionless transistor
  • Linearity
  • nanowire
  • regrowth source/drain

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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