In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - Design Automation Conference|
|State||Published - 1996|
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering