iCET: A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips

Yi Kan Cheng, Chin Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalArticle

Abstract

In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.

Original languageEnglish (US)
Pages (from-to)548-551
Number of pages4
JournalProceedings - Design Automation Conference
StatePublished - 1996

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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