Abstract
In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 548-551 |
| Number of pages | 4 |
| Journal | Proceedings - Design Automation Conference |
| State | Published - 1996 |
| Event | Proceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA Duration: Jun 3 1996 → Jun 7 1996 |
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering