iCET: A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips

Yi Kan Cheng, Chin Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalArticle

Abstract

In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.

Original languageEnglish (US)
Pages (from-to)548-551
Number of pages4
JournalProceedings - Design Automation Conference
StatePublished - 1996

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Packaging materials
Networks (circuits)
Transistors
Simulators
Boundary conditions
Temperature
Hot Temperature

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

iCET : A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips. / Cheng, Yi Kan; Teng, Chin Chi; Dharchoudhury, Abhijit; Rosenbaum, Elyse; Kang, Sung Mo.

In: Proceedings - Design Automation Conference, 1996, p. 548-551.

Research output: Contribution to journalArticle

Cheng, Yi Kan ; Teng, Chin Chi ; Dharchoudhury, Abhijit ; Rosenbaum, Elyse ; Kang, Sung Mo. / iCET : A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips. In: Proceedings - Design Automation Conference. 1996 ; pp. 548-551.
@article{82f0692815114378abe879b5f225af11,
title = "iCET: A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips",
abstract = "In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.",
author = "Cheng, {Yi Kan} and Teng, {Chin Chi} and Abhijit Dharchoudhury and Elyse Rosenbaum and Kang, {Sung Mo}",
year = "1996",
language = "English (US)",
pages = "548--551",
journal = "Proceedings - Design Automation Conference",
issn = "0738-100X",

}

TY - JOUR

T1 - iCET

T2 - A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips

AU - Cheng, Yi Kan

AU - Teng, Chin Chi

AU - Dharchoudhury, Abhijit

AU - Rosenbaum, Elyse

AU - Kang, Sung Mo

PY - 1996

Y1 - 1996

N2 - In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.

AB - In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.

UR - http://www.scopus.com/inward/record.url?scp=0029698052&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029698052&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0029698052

SP - 548

EP - 551

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

SN - 0738-100X

ER -