Boolean Satisfiability (SAT)-based routing has unique advantages over conventional one-net-at-a-time approaches such as simultaneous net embedding or routability decision. Yet SAT-based routing has been criticized for scalability issues. On the other hand, geometric search routing algorithms, even with extensive rip-up-reroute capabilities, have difficulty achieving routing solution convergence when a problem has tight routing constraints. In this paper, we revisit the SAT-based routing idea for FPGA routing, and propose a new hybrid algorithm that integrates SAT-based FPGA routing with a conventional geometric search FPGA router. The advantages of such a combination are twofold: 1) the scalability handicap of SAT-based routing is overcome due to the path pruning techniques of the geometric search algorithm, and 2) more concrete routability decisions can be made thus achieving the convergence, because the SAT-based technique considers simultaneously any paths in the history of iterative routings. The proposed algorithm named search-SAT is implemented and applied to real-world industry circuits. Preliminary experimental results show "search-SAT" is a more viable routing technique than any earlier SAT-based routing approach.