Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis

Keith Campbell, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen

Research output: Contribution to journalArticle

Abstract

Validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address the validation and debug of hardware accelerators. High-level synthesis (HLS) is a promising technique to rapidly create customized hardware accelerators. In this paper, we present the hybrid quick error detection (H-QED) approach that overcomes validation and debug challenges for hardware accelerators by leveraging HLS techniques in both the presilicon and post-silicon stages. H-QED improves error detection latencies (time elapsed from when a bug is activated to when it is detected) by 2-5 orders of magnitude with one cycle latencies in presilicon scenarios and bug coverage threefold higher compared to traditional validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs an 8% accelerator area overhead with negligible silicon performance impact for post-silicon stage, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED.

Original languageEnglish (US)
Article number8360082
Pages (from-to)1345-1358
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume38
Issue number7
DOIs
StatePublished - Jul 2019

Fingerprint

Error detection
Particle accelerators
Hardware
Silicon
High level synthesis
System-on-chip
Energy efficiency

Keywords

  • Automation
  • co-simulation
  • debug
  • detection latency
  • electrical bug
  • hardware
  • high-level synthesis (HLS)
  • hybrid hashing
  • hybrid tracing
  • logic bug
  • post-silicon
  • presilicon
  • simulation
  • software
  • system modeling
  • testing
  • validation

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Hybrid Quick Error Detection : Validation and Debug of SoCs Through High-Level Synthesis. / Campbell, Keith; Lin, David; He, Leon; Yang, Liwei; Gurumani, Swathi T.; Rupnow, Kyle; Mitra, Subhasish; Chen, Deming.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 7, 8360082, 07.2019, p. 1345-1358.

Research output: Contribution to journalArticle

Campbell, Keith ; Lin, David ; He, Leon ; Yang, Liwei ; Gurumani, Swathi T. ; Rupnow, Kyle ; Mitra, Subhasish ; Chen, Deming. / Hybrid Quick Error Detection : Validation and Debug of SoCs Through High-Level Synthesis. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 ; Vol. 38, No. 7. pp. 1345-1358.
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