Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis princIPles

Keyphrases

• High-level Synthesis 100%
• Debugging 100%
• Quick Error Detection 100%
• Hardware Accelerator 66%
• Post-silicon Validation 66%
• Post-silicon Debug 50%
• System-on-chip 33%
• Order of Magnitude 16%
• Detection Method 16%
• Complex Varieties 16%
• Synthesis Methods 16%
• System Performance 16%
• Impact Performance 16%
• System Energy 16%
• Performance Efficiency 16%
• Energy Efficiency 16%
• Intrusiveness 16%
• Chip-level 16%
• Time Elapsed 16%
• Method Validation 16%
• Latency Time 16%
• Benchmark Suite 16%
• Area Overhead 16%
• Error Latency 16%
• Dennard Scaling 16%
• Customized Hardware 16%

Computer Science

• High Level Synthesis 100%
• Error Detection 100%
• Hardware Accelerator 57%
• Silicon Validation 57%
• System-on-Chip 28%
• Systems Performance 14%
• Energy Efficiency 14%
• Performance Impact 14%
• Validation Technique 14%
• Synthesis Technique 14%
• Dennard Scaling 14%