Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis princIPles

Keith A. Campbell, David Lin, Subhasish Mitra, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Post-silicon validation and debug challenges of system-on-chIPs (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address post-silicon validation and debug of hardware accelerators. High-level synthesis (HLS) is a promising technique to rapidly create customized hardware accelerators. In this paper, we present the Hybrid Quick Error Detection (H-QED) approach that overcomes post-silicon validation and debug challenges for hardware accelerators by leveraging HLS techniques. H-QED improves error detection latencies (time elapsed from when a bug is activated to when it manifests as an observable failure) by 2 orders of magnitude and bug coverage 3-fold compared to traditional post-silicon validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs less than 2% chIP-level area overhead with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED.

Original languageEnglish (US)
Title of host publication2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450335201
DOIs
StatePublished - Jul 24 2015
Event52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States
Duration: Jun 7 2015Jun 11 2015

Publication series

NameProceedings - Design Automation Conference
Volume2015-July
ISSN (Print)0738-100X

Other

Other52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
CountryUnited States
CitySan Francisco
Period6/7/156/11/15

Keywords

  • C simulation
  • Post-silicon validation
  • accelerators
  • high-level synthesis
  • logic bugs
  • signature generation
  • timing errors

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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  • Cite this

    Campbell, K. A., Lin, D., Mitra, S., & Chen, D. (2015). Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis princIPles. In 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 [7167237] (Proceedings - Design Automation Conference; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2744769.2744853