Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors

Hongyin Luo, Shaojun Wei, Deming Chen, Donghui Guo

Research output: Contribution to journalArticlepeer-review

Abstract

Large-scale chip-multiprocessors (CMPs) need a scalable communication structure characterized by low cost, low power, and high performance to meet their on-chip communication requirements. This paper presents a hybrid circuit-switched (HCS) network for on-chip communication in the large-scale CMPs. The HCS network, which is Advanced Microcontroller Bus Architecture (AMBA) compatible, is composed of bufferless switches, pipeline channels, and network interfaces. Furthermore, packets are transferred in a hybrid transmission scheme. If a message has only one packet, the transmission scheme for this message is packet switching. Conversely, if a message contains multiple packets, the transmission scheme for this message is circuit switching. We evaluate HCS networks with different channel depths and then compare the HCS network with the Stanford elastic buffer (EB) network. Our results show that the HCS network with two-depth channel requires 83% less power and occupies 32% less area compared with the EB network. Furthermore, under maximum frequency and single traffic, the HCS network with two-depth channel provides 37% lower zero-load latency, 390% higher maximum throughput per unit power, and 19% higher maximum throughput per unit area compared with the EB network.

Original languageEnglish (US)
Pages (from-to)2818-2830
Number of pages13
JournalJournal of Parallel and Distributed Computing
Volume74
Issue number9
DOIs
StatePublished - Sep 2014

Keywords

  • AMBA compatibility
  • Chip-multiprocessors
  • Hybrid packet-circuit switching
  • Network-on-chip
  • Pipeline channel

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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