TY - GEN
T1 - HPVM-HDC
T2 - 52nd Annual International Symposium on Computer Architecture, ISCA 2025
AU - Arbore, Russel
AU - Routh, Xavier
AU - Noor, Abdul Rafae
AU - Kothari, Akash
AU - Yang, Haichao
AU - Xu, Weihong
AU - Pinge, Sumukh
AU - Zhou, Minxuan
AU - Rosing, Tajana
AU - Adve, Vikram
N1 - We thank the anonymous reviewers for their helpful feedback on this paper. This work was supported by funding from PRISM, one of the seven centers in JUMP 2.0, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.
PY - 2025/6/21
Y1 - 2025/6/21
N2 - Hyperdimensional Computing (HDC), a technique inspired by cognitive models of computation, has been proposed as an efficient and robust alternative basis for machine learning. HDC programs are often manually written in low-level and target specific languages targeting CPUs, GPUs, and FPGAs-these codes cannot be easily retargeted onto HDC-specific accelerators. No previous programming system enables productive development of HDC programs and generates efficient code for several hardware targets. We propose a heterogeneous programming system for HDC: a novel programming language, HDC++, for writing applications using a unified programming model, including HDC-specific primitives to improve programmability, and a heterogeneous compiler, HPVM-HDC, that provides an intermediate representation for compiling HDC programs to many hardware targets. We implement two tuning optimizations, automatic binarization and reduction perforation, that exploit the error resilient nature of HDC. Our evaluation shows that HPVM-HDC generates performance-competitive code for CPUs and GPUs, achieving a geomean speed-up of 1.17x over optimized baseline CUDA implementations with a geomean reduction in total lines of code of 1.6x across CPUs and GPUs. Additionally, HPVM-HDC targets an HDC Digital ASIC and an HDC ReRAM accelerator simulator, enabling the first execution of HDC applications on these devices.
AB - Hyperdimensional Computing (HDC), a technique inspired by cognitive models of computation, has been proposed as an efficient and robust alternative basis for machine learning. HDC programs are often manually written in low-level and target specific languages targeting CPUs, GPUs, and FPGAs-these codes cannot be easily retargeted onto HDC-specific accelerators. No previous programming system enables productive development of HDC programs and generates efficient code for several hardware targets. We propose a heterogeneous programming system for HDC: a novel programming language, HDC++, for writing applications using a unified programming model, including HDC-specific primitives to improve programmability, and a heterogeneous compiler, HPVM-HDC, that provides an intermediate representation for compiling HDC programs to many hardware targets. We implement two tuning optimizations, automatic binarization and reduction perforation, that exploit the error resilient nature of HDC. Our evaluation shows that HPVM-HDC generates performance-competitive code for CPUs and GPUs, achieving a geomean speed-up of 1.17x over optimized baseline CUDA implementations with a geomean reduction in total lines of code of 1.6x across CPUs and GPUs. Additionally, HPVM-HDC targets an HDC Digital ASIC and an HDC ReRAM accelerator simulator, enabling the first execution of HDC applications on these devices.
KW - Compilers
KW - Heterogeneous Systems
KW - Hyperdimensional Computing
UR - https://www.scopus.com/pages/publications/105009584713
UR - https://www.scopus.com/pages/publications/105009584713#tab=citedBy
U2 - 10.1145/3695053.3731095
DO - 10.1145/3695053.3731095
M3 - Conference contribution
AN - SCOPUS:105009584713
T3 - Proceedings - International Symposium on Computer Architecture
SP - 1342
EP - 1355
BT - ISCA 2025 - Proceedings of the 52nd Annual International Symposium on Computer Architecture
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 21 June 2025 through 25 June 2025
ER -