HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality

Wen Mei Hwu, Yale N. Patt

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Our recent work in microarchitecture has identified a new model of execution, restricted data Bow, in which data flow techniques are used to coordinate out-of-order execution of sequential instruction streams. We believe that the restricted data flow model has great potential for implementing very high performance computing engines. This paper defines a minimal functionality variant of our model, which we are calling HPSm. The instruction set, data path, timing and control of HPSm are all described. A simulator for HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. We report the measurements obtained from these benchmarks, along with the measurements obtained for the Berkeley RISC II. The resulb are encouraging.

Original languageEnglish (US)
Title of host publicationISCA 1998 - 25 years of the International Symposia on Computer Architecture (Selected Papers)
EditorsGurindar S. Sohi
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages9
ISBN (Electronic)9781581130584
StatePublished - Aug 1 1998
Externally publishedYes
Event25th International Symposium on Computer Architecture, ISCA 1998 - Barcelona, Spain
Duration: Jun 27 1998Jul 2 1998

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


Conference25th International Symposium on Computer Architecture, ISCA 1998

ASJC Scopus subject areas

  • Hardware and Architecture

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