HPSM, A HIGH PERFORMANCE RESTRICTED DATA FLOW ARCHITECTURE HAVING MINIMAL FUNCTIONALITY.

Wen-Mei W Hwu, Yale N. Patt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data-flow techniques are used to coordinate out-of-order execution of sequential instruction streams. It is believed that the restricted-data-flow model has great potential for implementing high-performance computing engines. A minimal functionality variant of the model, called HPSm, is defined. The instruction set, data path, timing and control of HPSm are described. A simulator of HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. Measurements obtained from these benchmarks, along with measurements obtained for the Berkeley RISC II, are reported.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherIEEE
Pages297-306
Number of pages10
ISBN (Print)081860719X
StatePublished - 1986
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Hwu, W-M. W., & Patt, Y. N. (1986). HPSM, A HIGH PERFORMANCE RESTRICTED DATA FLOW ARCHITECTURE HAVING MINIMAL FUNCTIONALITY. In Conference Proceedings - Annual Symposium on Computer Architecture (pp. 297-306). IEEE.