Abstract
Recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data-flow techniques are used to coordinate out-of-order execution of sequential instruction streams. It is believed that the restricted-data-flow model has great potential for implementing high-performance computing engines. A minimal functionality variant of the model, called HPSm, is defined. The instruction set, data path, timing and control of HPSm are described. A simulator of HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. Measurements obtained from these benchmarks, along with measurements obtained for the Berkeley RISC II, are reported.
| Original language | English (US) |
|---|---|
| Title of host publication | Conference Proceedings - Annual Symposium on Computer Architecture |
| Publisher | IEEE |
| Pages | 297-306 |
| Number of pages | 10 |
| ISBN (Print) | 081860719X |
| State | Published - 1986 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
HPSM, A HIGH PERFORMANCE RESTRICTED DATA FLOW ARCHITECTURE HAVING MINIMAL FUNCTIONALITY. / Hwu, Wen-Mei W; Patt, Yale N.
Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, 1986. p. 297-306.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - HPSM, A HIGH PERFORMANCE RESTRICTED DATA FLOW ARCHITECTURE HAVING MINIMAL FUNCTIONALITY.
AU - Hwu, Wen-Mei W
AU - Patt, Yale N.
PY - 1986
Y1 - 1986
N2 - Recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data-flow techniques are used to coordinate out-of-order execution of sequential instruction streams. It is believed that the restricted-data-flow model has great potential for implementing high-performance computing engines. A minimal functionality variant of the model, called HPSm, is defined. The instruction set, data path, timing and control of HPSm are described. A simulator of HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. Measurements obtained from these benchmarks, along with measurements obtained for the Berkeley RISC II, are reported.
AB - Recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data-flow techniques are used to coordinate out-of-order execution of sequential instruction streams. It is believed that the restricted-data-flow model has great potential for implementing high-performance computing engines. A minimal functionality variant of the model, called HPSm, is defined. The instruction set, data path, timing and control of HPSm are described. A simulator of HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. Measurements obtained from these benchmarks, along with measurements obtained for the Berkeley RISC II, are reported.
UR - http://www.scopus.com/inward/record.url?scp=0022584031&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0022584031&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0022584031
SN - 081860719X
SP - 297
EP - 306
BT - Conference Proceedings - Annual Symposium on Computer Architecture
PB - IEEE
ER -