Recent work in microarchitecture has identified a new model of execution, restricted data flow, in which data-flow techniques are used to coordinate out-of-order execution of sequential instruction streams. It is believed that the restricted-data-flow model has great potential for implementing high-performance computing engines. A minimal functionality variant of the model, called HPSm, is defined. The instruction set, data path, timing and control of HPSm are described. A simulator of HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. Measurements obtained from these benchmarks, along with measurements obtained for the Berkeley RISC II, are reported.
|Original language||English (US)|
|Title of host publication||Conference Proceedings - Annual Symposium on Computer Architecture|
|Number of pages||10|
|State||Published - 1986|
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