Hot carrier effects in nMOSFETs in 0.1μm CMOS technology

E. Li, Elyse Rosenbaum, J. Tao, G. C.F. Yeap, M. R. Lin, P. Fang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent studies show that, for a given technology, as the effective channel length is scaled down towards 0.1 μm, the worst case hot carrier stress condition for nMOSFETs switches from Ib,peak (peak substrate current bias condition) to Vg = Vd. In this paper, we demonstrate that the worst case stress condition is determined by the ratio of qq to qq. Post-metallization anneal in deuterium similarly improves hot carrier lifetime under bias at Ib,peak and Vg = Vd.

Original languageEnglish (US)
Title of host publicationAnnual Proceedings - Reliability Physics (Symposium)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-258
Number of pages6
ISBN (Print)0780352203
StatePublished - Jan 1 1999
EventProceedings of the 1999 37th Annual IEEE International Reliability Physics Symposium - San Diego, CA, USA
Duration: Mar 23 1999Mar 25 1999

Publication series

NameAnnual Proceedings - Reliability Physics (Symposium)
ISSN (Print)0099-9512

Other

OtherProceedings of the 1999 37th Annual IEEE International Reliability Physics Symposium
CitySan Diego, CA, USA
Period3/23/993/25/99

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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