Strained Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are promising candidates for next-generation complementary MOS (CMOS) technology. While electron mobility enhancements in these heterostructures have been thoroughly investigated, hole mobility enhancements have not been explored in as much detail. In this study, we investigate the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition. We show that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices. These results represent peak hole mobilities above 200cm 2/V-S. Furthermore, we demonstrate that hole mobility in strained Si/relaxed Si 0.7Ge 0.3 heterostructures displays no strong dependence on strained layer thickness, indicating that strain is the primary variable controlling channel mobility in strained Si p-type MOSFETs (p-MOSFETs). We then compare these results to previous studies on channel mobility in strained Si n-type MOSFETs. Finally, we measure channel mobility in Si 1-yGe y (y=0.1, 0.2, 0.3, and 0.4) surface channel MOSFETs under equal tensile strain and directly compare electron and hole mobility degradation due to alloy scattering. In agreement with theoretical predictions, electron mobility is degraded more severely than hole mobility in these heterostructures. Though these heterostructures were capped with very thin strained Si layers to preserve the high-quality MOS interface, electrical measurements indicate that interface state density increases significantly for 30% Ge and 40% Ge alloy channels. Overall, these results demonstrate the possibility of obtaining symmetric electron and hole mobility enhancements in strained Si CMOS technology and present a comprehensive evaluation of heterostructure channel engineering in strained Si p-MOSFETs.
ASJC Scopus subject areas
- Physics and Astronomy(all)