HLS-Based Acceleration Framework for Deep Convolutional Neural Networks

Ashish Misra, Volodymyr Kindratenko

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Deep Neural Networks (DNNs) have been successfully applied in many fields. Considering performance, flexibility, and energy efficiency, Field Programmable Gate Array (FPGA) based accelerator for DNNs is a promising solution. The existing frameworks however lack the possibility of reusability and friendliness to design a new network with minimum efforts. Modern high-level synthesis (HLS) tools greatly reduce the turnaround time of designing and implementing complex FPGA-based accelerators. This paper presents a framework for hardware accelerator for DNNs using high level specification. A novel architecture is introduced that maximizes data reuse and external memory bandwidth. This framework allows to generate a scalable HLS code for a given pre-trained model that can be mapped to different FPGA platforms. Various HLS compiler optimizations have been applied to the code to produce efficient implementation and high resource utilization. The framework achieves a peak performance of 23 frames per second for SqueezeNet on Xilinx Alveo u250 board.

Original languageEnglish (US)
Title of host publicationApplied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Proceedings
EditorsFernando Rincón, Jesús Barba, Julián Caba, Hayden K.H. So, Pedro Diniz
PublisherSpringer
Pages221-231
Number of pages11
ISBN (Print)9783030445331
DOIs
StatePublished - 2020
Event16th International Symposium on Applied Reconfigurable Computing, ARC 2020 - Toledo, Spain
Duration: Apr 1 2020Apr 3 2020

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume12083 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference16th International Symposium on Applied Reconfigurable Computing, ARC 2020
CountrySpain
CityToledo
Period4/1/204/3/20

Keywords

  • Accelerator design
  • FPGA
  • High level synthesis

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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