High-speed planar gaas nanowire arrays with f max > 75 GHz by wafer-scale bottom-up growth

Xin Miao, Kelson Chabak, Chen Zhang, Parsian K. Mohseni, Dennis Walker, Xiuling Li

Research output: Contribution to journalArticlepeer-review

Abstract

Wafer-scale defect-free planar III-V nanowire (NW) arrays with ∼100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

Original languageEnglish (US)
Pages (from-to)2780-2786
Number of pages7
JournalNano letters
Volume15
Issue number5
DOIs
StatePublished - May 13 2015

Keywords

  • Bottom-up
  • III-V
  • VLS
  • VLSI
  • nanowire
  • transistor

ASJC Scopus subject areas

  • Bioengineering
  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanical Engineering

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