HIGH-PERFORMANCE, LOW-TEMPERATURE SELF-ALIGNED GATE E/D PROCESS.

A high-performance, lightly-doped-drain (LDD) self-aligned gate FET (SAGFET) E/D process using a substitutional gate, a spacer and arsine overpressure annealing has been developed. The gate metal is formed at a low temperature after postimplantation annealing. Transconductance of 240 mS/mm and a K factor of 4. 4 mS/mm for a 1. 4 mu m multiplied by 20 mu m E-SAGFET with Vp equals 0. 1 V and a 32 mV standard deviation demultiplexer over a 3-in wafer has been demonstrated. An ECL-compatible gate array having 561 four-input NOR gates has been developed. Full functionality of an 8 multiplied by 8 multiplier, 8-bit multiplexer and standard deviation demultiplexer, and 8-bit adder and divider have all been demonstrated in personalized gate arrays. Fully loaded internal gate delay of 225 ps with 1. 5 mW dissipation and 5 ns 8 multiplied by 8 multiplication time have been realized using a 1. 4- mu m gate. Unloaded gate delay of 110 ps was demonstrated with a 1. 25- mu m gate. The E/D technology was based on a conservative, planarized two-level metallization using silicon nitride as an interlayer dielectric.