High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

M. Chudzik; B. Doris; R. Mo; J. Sleight; E. Cartier; C. Dewan; D. Park; H. Bu; W. Natzle; W. Yan; C. Ouyang; K. Henson; D. Boyd; S. Callegari; R. Carter; D. Casarotto; M. Gribelyuk; M. Hargrove; W. He; Y. Kim; B. Linder; N. Moumen; V. K. Paruchuri; J. Stathis; M. Steen; A. Vayshenker; X. Wang; S. Zafar; T. Ando; R. Iijima; M. Takayanagi; V. Narayanan; R. Wise; Y. Zhang; R. Divakaruni; M. Khare; T. C. Chen

doi:10.1109/VLSIT.2007.4339689

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

M. Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, C. Dewan, D. Park, H. Bu, W. Natzle, W. Yan, C. Ouyang, K. Henson, D. Boyd, S. Callegari, R. Carter, D. Casarotto, M. Gribelyuk, M. Hargrove, W. He, Y. KimB. Linder, N. Moumen, V. K. Paruchuri, J. Stathis, M. Steen, A. Vayshenker, X. Wang, S. Zafar, T. Ando, R. Iijima, M. Takayanagi, V. Narayanan, R. Wise, Y. Zhang, R. Divakaruni, M. Khare, T. C. Chen

Research output: Contribution to journal › Conference article › peer-review

Abstract

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest T_inv (<12Å) for BE nFET devices to-date, consistent with simulations showing the need for <14Å T_inv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T _inv (<13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

Original language	English (US)
Article number	4339689
Pages (from-to)	194-195
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2007.4339689
State	Published - 2007
Externally published	Yes
Event	2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan Duration: Jun 12 2007 → Jun 14 2007

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2007.4339689

Fingerprint Dive into the research topics of 'High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing'. Together they form a unique fingerprint.

Cite this

Chudzik, M., Doris, B., Mo, R., Sleight, J., Cartier, E., Dewan, C., Park, D., Bu, H., Natzle, W., Yan, W., Ouyang, C., Henson, K., Boyd, D., Callegari, S., Carter, R., Casarotto, D., Gribelyuk, M., Hargrove, M., He, W., ... Chen, T. C. (2007). High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing. Digest of Technical Papers - Symposium on VLSI Technology, 194-195. [4339689]. https://doi.org/10.1109/VLSIT.2007.4339689

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing. / Chudzik, M.; Doris, B.; Mo, R.; Sleight, J.; Cartier, E.; Dewan, C.; Park, D.; Bu, H.; Natzle, W.; Yan, W.; Ouyang, C.; Henson, K.; Boyd, D.; Callegari, S.; Carter, R.; Casarotto, D.; Gribelyuk, M.; Hargrove, M.; He, W.; Kim, Y.; Linder, B.; Moumen, N.; Paruchuri, V. K.; Stathis, J.; Steen, M.; Vayshenker, A.; Wang, X.; Zafar, S.; Ando, T.; Iijima, R.; Takayanagi, M.; Narayanan, V.; Wise, R.; Zhang, Y.; Divakaruni, R.; Khare, M.; Chen, T. C.

In: Digest of Technical Papers - Symposium on VLSI Technology, 2007, p. 194-195.

Research output: Contribution to journal › Conference article › peer-review

Chudzik, M, Doris, B, Mo, R, Sleight, J, Cartier, E, Dewan, C, Park, D, Bu, H, Natzle, W, Yan, W, Ouyang, C, Henson, K, Boyd, D, Callegari, S, Carter, R, Casarotto, D, Gribelyuk, M, Hargrove, M, He, W, Kim, Y, Linder, B, Moumen, N, Paruchuri, VK, Stathis, J, Steen, M, Vayshenker, A, Wang, X, Zafar, S, Ando, T, Iijima, R, Takayanagi, M, Narayanan, V, Wise, R, Zhang, Y, Divakaruni, R, Khare, M & Chen, TC 2007, 'High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing', Digest of Technical Papers - Symposium on VLSI Technology, pp. 194-195. https://doi.org/10.1109/VLSIT.2007.4339689

Chudzik, M. ; Doris, B. ; Mo, R. ; Sleight, J. ; Cartier, E. ; Dewan, C. ; Park, D. ; Bu, H. ; Natzle, W. ; Yan, W. ; Ouyang, C. ; Henson, K. ; Boyd, D. ; Callegari, S. ; Carter, R. ; Casarotto, D. ; Gribelyuk, M. ; Hargrove, M. ; He, W. ; Kim, Y. ; Linder, B. ; Moumen, N. ; Paruchuri, V. K. ; Stathis, J. ; Steen, M. ; Vayshenker, A. ; Wang, X. ; Zafar, S. ; Ando, T. ; Iijima, R. ; Takayanagi, M. ; Narayanan, V. ; Wise, R. ; Zhang, Y. ; Divakaruni, R. ; Khare, M. ; Chen, T. C. / High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing. In: Digest of Technical Papers - Symposium on VLSI Technology. 2007 ; pp. 194-195.

@article{ae1dc1582e694d7a818dfeeec77ab908,

title = "High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing",

abstract = "Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (<12{\AA}) for BE nFET devices to-date, consistent with simulations showing the need for <14{\AA} Tinv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T inv (<13{\AA}) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.",

author = "M. Chudzik and B. Doris and R. Mo and J. Sleight and E. Cartier and C. Dewan and D. Park and H. Bu and W. Natzle and W. Yan and C. Ouyang and K. Henson and D. Boyd and S. Callegari and R. Carter and D. Casarotto and M. Gribelyuk and M. Hargrove and W. He and Y. Kim and B. Linder and N. Moumen and Paruchuri, {V. K.} and J. Stathis and M. Steen and A. Vayshenker and X. Wang and S. Zafar and T. Ando and R. Iijima and M. Takayanagi and V. Narayanan and R. Wise and Y. Zhang and R. Divakaruni and M. Khare and Chen, {T. C.}",

year = "2007",

doi = "10.1109/VLSIT.2007.4339689",

language = "English (US)",

pages = "194--195",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 Symposium on VLSI Technology, VLSIT 2007 ; Conference date: 12-06-2007 Through 14-06-2007",

}

TY - JOUR

T1 - High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

AU - Chudzik, M.

AU - Doris, B.

AU - Mo, R.

AU - Sleight, J.

AU - Cartier, E.

AU - Dewan, C.

AU - Park, D.

AU - Bu, H.

AU - Natzle, W.

AU - Yan, W.

AU - Ouyang, C.

AU - Henson, K.

AU - Boyd, D.

AU - Callegari, S.

AU - Carter, R.

AU - Casarotto, D.

AU - Gribelyuk, M.

AU - Hargrove, M.

AU - He, W.

AU - Kim, Y.

AU - Linder, B.

AU - Moumen, N.

AU - Paruchuri, V. K.

AU - Stathis, J.

AU - Steen, M.

AU - Vayshenker, A.

AU - Wang, X.

AU - Zafar, S.

AU - Ando, T.

AU - Iijima, R.

AU - Takayanagi, M.

AU - Narayanan, V.

AU - Wise, R.

AU - Zhang, Y.

AU - Divakaruni, R.

AU - Khare, M.

AU - Chen, T. C.

PY - 2007

Y1 - 2007

N2 - Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (<12Å) for BE nFET devices to-date, consistent with simulations showing the need for <14Å Tinv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T inv (<13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

AB - Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (<12Å) for BE nFET devices to-date, consistent with simulations showing the need for <14Å Tinv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T inv (<13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

UR - http://www.scopus.com/inward/record.url?scp=36448952970&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=36448952970&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2007.4339689

DO - 10.1109/VLSIT.2007.4339689

M3 - Conference article

AN - SCOPUS:36448952970

SP - 194

EP - 195

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

SN - 0743-1562

M1 - 4339689

T2 - 2007 Symposium on VLSI Technology, VLSIT 2007

Y2 - 12 June 2007 through 14 June 2007

ER -

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Cite this