High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

M. Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, C. Dewan, D. Park, H. Bu, W. Natzle, W. Yan, C. Ouyang, K. Henson, D. Boyd, S. Callegari, R. Carter, D. Casarotto, M. Gribelyuk, M. Hargrove, W. He, Y. KimB. Linder, N. Moumen, V. K. Paruchuri, J. Stathis, M. Steen, A. Vayshenker, X. Wang, S. Zafar, T. Ando, R. Iijima, M. Takayanagi, V. Narayanan, R. Wise, Y. Zhang, R. Divakaruni, M. Khare, T. C. Chen

Research output: Contribution to journalConference articlepeer-review


Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (<12Å) for BE nFET devices to-date, consistent with simulations showing the need for <14Å Tinv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T inv (<13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

Original languageEnglish (US)
Article number4339689
Pages (from-to)194-195
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 2007
Externally publishedYes
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: Jun 12 2007Jun 14 2007

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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