High-performance CUDA kernel execution on FPGAs

Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen Mei W. Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to efficiently map the exposed parallelism in CUDA kernels onto reconfigurable devices. The use of the CUDA programming model offers the advantage of a common programming interface for exploiting parallelism on two very different types of accelerators - FPGAs and GPUs. Moreover, by leveraging the advanced synthesis capabilities of AutoPilot we enable efficient exploitation of the FPGA configurability for application specific acceleration. Our flow is based on a compilation process that transforms the SPMD CUDA thread blocks into high-concurrency AutoPilot-C code. We provide an overview of our CUDA-to-FPGA flow and demonstrate the highly competitive performance of the generated multi-core accelerators.

Original languageEnglish (US)
Title of host publicationICS'09 - Proceedings of the 23rd International Conference on Supercomputing
Number of pages2
StatePublished - 2009
Event23rd International Conference on Supercomputing, ICS'09 - Yorktown Heights, NY, United States
Duration: Jun 8 2009Jun 12 2009

Publication series

NameProceedings of the International Conference on Supercomputing


Other23rd International Conference on Supercomputing, ICS'09
Country/TerritoryUnited States
CityYorktown Heights, NY


  • CUDA programming model
  • Coarse-grained parallelism
  • FPGA
  • GPU
  • High performance computing
  • High-level synthesis

ASJC Scopus subject areas

  • General Computer Science


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