TY - GEN
T1 - High-Performance CMOS TIA for Data Center Optical Interconnects
AU - Lakshmikumar, Kadaba R.
AU - Kurylak, Alexander
AU - Kumar Nandwana, Romesh
AU - Das, Bibhu
AU - Pampanin, Joe
AU - Boccuzzi, Vito
AU - Kumar Hanumolu, Pavan
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - An overview of Silicon Photonics and SiGe bipolar TIAs are presented for data center links. CMOS inverter-based TIA circuit topologies for high-bandwidth, low-noise, low-power, and high-linearity are discussed in brief. A design methodology to achieve the best overall receiver sensitivity is presented for a standalone TIA and a TIA codesigned with a DSP. The codesigned TIA methodology is validated using a 106.25 Gbps PAM-4 TIA prototype. Designed in a 16 nm FinFET CMOS process, the TIA with a transimpedance gain of 76 dBΩ has a range of 16 dBΩ. The TIA consumes 103.6 mW, has a -3 dB bandwidth of 18.4 GHz, an input-referred noise of 1.58 μA, and a noise density of 9.7 pA/√Hz.
AB - An overview of Silicon Photonics and SiGe bipolar TIAs are presented for data center links. CMOS inverter-based TIA circuit topologies for high-bandwidth, low-noise, low-power, and high-linearity are discussed in brief. A design methodology to achieve the best overall receiver sensitivity is presented for a standalone TIA and a TIA codesigned with a DSP. The codesigned TIA methodology is validated using a 106.25 Gbps PAM-4 TIA prototype. Designed in a 16 nm FinFET CMOS process, the TIA with a transimpedance gain of 76 dBΩ has a range of 16 dBΩ. The TIA consumes 103.6 mW, has a -3 dB bandwidth of 18.4 GHz, an input-referred noise of 1.58 μA, and a noise density of 9.7 pA/√Hz.
KW - Broadband
KW - CMOS inverter-based amplifiers
KW - PAM-4
KW - Silicon Photonics
KW - dynamic voltage scaling (DVS)
KW - high linearity
KW - optical links
KW - transimpedance amplifier (TIA)
UR - http://www.scopus.com/inward/record.url?scp=85150045328&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85150045328&partnerID=8YFLogxK
U2 - 10.1109/BCICTS53451.2022.10051698
DO - 10.1109/BCICTS53451.2022.10051698
M3 - Conference contribution
AN - SCOPUS:85150045328
T3 - 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2022
SP - 9
EP - 16
BT - 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2022
Y2 - 16 October 2022 through 19 October 2022
ER -