High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta, K. Miyamoto, M. Angyal, H. V. Meer, K. McStay, I. Ahsan, S. Allen, A. Azuma, M. Belyansky, R. V. Bentum, J. Cheng, D. Chidambarrao, B. Dirahoui, M. Fukasawa, M. Gerhardt, M. Gribelyuk, S. Halle, H. HarifuchiD. Harmon, J. Heaps-Nelson, H. Hichri, K. Ida, M. Inohara, K. Inoue, K. Jenkins, T. Kawamura, B. Kim, S. K. Ku, M. Kumar, S. Lane, L. Liebmann, R. Logan, I. Melville, K. Miyashita, A. Mocuta, P. O'Neil, M. F. Ng, T. Nogami, A. Nomura, C. Norris, E. Nowak, M. Ono, S. Panda, C. Penny, C. Radens, R. Ramachandran, A. Ray, S. H. Rhee, D. Ryan, T. Shinohara, G. Sudo, F. Sugaya, J. Strane, Y. Tan, L. Tsou, L. Wang, F. Wirbeleit, S. Wu, T. Yamashita, H. Yan, Q. Ye, D. Yoneyama, N. Zamdmer, H. Zhong, H. Zhu, W. Zhu, P. Agnello, S. Bukofsky, G. Bronner, E. Crabbé, G. Freeman, S. F. Huang, T. Ivers, H. Kuroda, D. McHerron, J. Pellerin, Y. Toyoshima, S. Subbanna, N. Kepler, L. Su

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm 2 SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Original languageEnglish (US)
Title of host publication2005 Symposium on VLSI Technology, Digest of Technical Papers
Pages126-127
Number of pages2
DOIs
StatePublished - 2005
Externally publishedYes
Event2005 Symposium on VLSI Technology - Kyoto, Japan
Duration: Jun 14 2005Jun 14 2005

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2005
ISSN (Print)0743-1562

Other

Other2005 Symposium on VLSI Technology
CountryJapan
CityKyoto
Period6/14/056/14/05

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Leobandung, E., Nayakama, H., Mocuta, D., Miyamoto, K., Angyal, M., Meer, H. V., McStay, K., Ahsan, I., Allen, S., Azuma, A., Belyansky, M., Bentum, R. V., Cheng, J., Chidambarrao, D., Dirahoui, B., Fukasawa, M., Gerhardt, M., Gribelyuk, M., Halle, S., ... Su, L. (2005). High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell. In 2005 Symposium on VLSI Technology, Digest of Technical Papers (pp. 126-127). [1469238] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2005). https://doi.org/10.1109/.2005.1469238