High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung; H. Nayakama; D. Mocuta; K. Miyamoto; M. Angyal; H. V. Meer; K. McStay; I. Ahsan; S. Allen; A. Azuma; M. Belyansky; R. V. Bentum; J. Cheng; D. Chidambarrao; B. Dirahoui; M. Fukasawa; M. Gerhardt; M. Gribelyuk; S. Halle; H. Harifuchi; D. Harmon; J. Heaps-Nelson; H. Hichri; K. Ida; M. Inohara; K. Inoue; K. Jenkins; T. Kawamura; B. Kim; S. K. Ku; M. Kumar; S. Lane; L. Liebmann; R. Logan; I. Melville; K. Miyashita; A. Mocuta; P. O'Neil; M. F. Ng; T. Nogami; A. Nomura; C. Norris; E. Nowak; M. Ono; S. Panda; C. Penny; C. Radens; R. Ramachandran; A. Ray; S. H. Rhee; D. Ryan; T. Shinohara; G. Sudo; F. Sugaya; J. Strane; Y. Tan; L. Tsou; L. Wang; F. Wirbeleit; S. Wu; T. Yamashita; H. Yan; Q. Ye; D. Yoneyama; N. Zamdmer; H. Zhong; H. Zhu; W. Zhu; P. Agnello; S. Bukofsky; G. Bronner; E. Crabbé; G. Freeman; S. F. Huang; T. Ivers; H. Kuroda; D. McHerron; J. Pellerin; Y. Toyoshima; S. Subbanna; N. Kepler; L. Su

doi:10.1109/.2005.1469238

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta, K. Miyamoto, M. Angyal, H. V. Meer, K. McStay, I. Ahsan, S. Allen, A. Azuma, M. Belyansky, R. V. Bentum, J. Cheng, D. Chidambarrao, B. Dirahoui, M. Fukasawa, M. Gerhardt, M. Gribelyuk, S. Halle, H. HarifuchiD. Harmon, J. Heaps-Nelson, H. Hichri, K. Ida, M. Inohara, K. Inoue, K. Jenkins, T. Kawamura, B. Kim, S. K. Ku, M. Kumar, S. Lane, L. Liebmann, R. Logan, I. Melville, K. Miyashita, A. Mocuta, P. O'Neil, M. F. Ng, T. Nogami, A. Nomura, C. Norris, E. Nowak, M. Ono, S. Panda, C. Penny, C. Radens, R. Ramachandran, A. Ray, S. H. Rhee, D. Ryan, T. Shinohara, G. Sudo, F. Sugaya, J. Strane, Y. Tan, L. Tsou, L. Wang, F. Wirbeleit, S. Wu, T. Yamashita, H. Yan, Q. Ye, D. Yoneyama, N. Zamdmer, H. Zhong, H. Zhu, W. Zhu, P. Agnello, S. Bukofsky, G. Bronner, E. Crabbé, G. Freeman, S. F. Huang, T. Ivers, H. Kuroda, D. McHerron, J. Pellerin, Y. Toyoshima, S. Subbanna, N. Kepler, L. Su

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm ² SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Original language	English (US)
Title of host publication	2005 Symposium on VLSI Technology, Digest of Technical Papers
Pages	126-127
Number of pages	2
DOIs	https://doi.org/10.1109/.2005.1469238
State	Published - 2005
Externally published	Yes
Event	2005 Symposium on VLSI Technology - Kyoto, Japan Duration: Jun 14 2005 → Jun 14 2005

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2005
ISSN (Print)	0743-1562

Other

Other	2005 Symposium on VLSI Technology
Country/Territory	Japan
City	Kyoto
Period	6/14/05 → 6/14/05

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/.2005.1469238

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Leobandung, E., Nayakama, H., Mocuta, D., Miyamoto, K., Angyal, M., Meer, H. V., McStay, K., Ahsan, I., Allen, S., Azuma, A., Belyansky, M., Bentum, R. V., Cheng, J., Chidambarrao, D., Dirahoui, B., Fukasawa, M., Gerhardt, M., Gribelyuk, M., Halle, S., ... Su, L. (2005). High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell. In 2005 Symposium on VLSI Technology, Digest of Technical Papers (pp. 126-127). Article 1469238 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2005). https://doi.org/10.1109/.2005.1469238

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell. / Leobandung, E.; Nayakama, H.; Mocuta, D. et al.
2005 Symposium on VLSI Technology, Digest of Technical Papers. 2005. p. 126-127 1469238 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Leobandung, E, Nayakama, H, Mocuta, D, Miyamoto, K, Angyal, M, Meer, HV, McStay, K, Ahsan, I, Allen, S, Azuma, A, Belyansky, M, Bentum, RV, Cheng, J, Chidambarrao, D, Dirahoui, B, Fukasawa, M, Gerhardt, M, Gribelyuk, M, Halle, S, Harifuchi, H, Harmon, D, Heaps-Nelson, J, Hichri, H, Ida, K, Inohara, M, Inoue, K, Jenkins, K, Kawamura, T, Kim, B, Ku, SK, Kumar, M, Lane, S, Liebmann, L, Logan, R, Melville, I, Miyashita, K, Mocuta, A, O'Neil, P, Ng, MF, Nogami, T, Nomura, A, Norris, C, Nowak, E, Ono, M, Panda, S, Penny, C, Radens, C, Ramachandran, R, Ray, A, Rhee, SH, Ryan, D, Shinohara, T, Sudo, G, Sugaya, F, Strane, J, Tan, Y, Tsou, L, Wang, L, Wirbeleit, F, Wu, S, Yamashita, T, Yan, H, Ye, Q, Yoneyama, D, Zamdmer, N, Zhong, H, Zhu, H, Zhu, W, Agnello, P, Bukofsky, S, Bronner, G, Crabbé, E, Freeman, G, Huang, SF, Ivers, T, Kuroda, H, McHerron, D, Pellerin, J, Toyoshima, Y, Subbanna, S, Kepler, N & Su, L 2005, High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell. in 2005 Symposium on VLSI Technology, Digest of Technical Papers., 1469238, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2005, pp. 126-127, 2005 Symposium on VLSI Technology, Kyoto, Japan, 6/14/05. https://doi.org/10.1109/.2005.1469238

@inproceedings{4a2284e2aa1146c48b0e51088215204f,

title = "High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell",

abstract = "A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm 2 SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.",

author = "E. Leobandung and H. Nayakama and D. Mocuta and K. Miyamoto and M. Angyal and Meer, {H. V.} and K. McStay and I. Ahsan and S. Allen and A. Azuma and M. Belyansky and Bentum, {R. V.} and J. Cheng and D. Chidambarrao and B. Dirahoui and M. Fukasawa and M. Gerhardt and M. Gribelyuk and S. Halle and H. Harifuchi and D. Harmon and J. Heaps-Nelson and H. Hichri and K. Ida and M. Inohara and K. Inoue and K. Jenkins and T. Kawamura and B. Kim and Ku, {S. K.} and M. Kumar and S. Lane and L. Liebmann and R. Logan and I. Melville and K. Miyashita and A. Mocuta and P. O'Neil and Ng, {M. F.} and T. Nogami and A. Nomura and C. Norris and E. Nowak and M. Ono and S. Panda and C. Penny and C. Radens and R. Ramachandran and A. Ray and Rhee, {S. H.} and D. Ryan and T. Shinohara and G. Sudo and F. Sugaya and J. Strane and Y. Tan and L. Tsou and L. Wang and F. Wirbeleit and S. Wu and T. Yamashita and H. Yan and Q. Ye and D. Yoneyama and N. Zamdmer and H. Zhong and H. Zhu and W. Zhu and P. Agnello and S. Bukofsky and G. Bronner and E. Crabb{\'e} and G. Freeman and Huang, {S. F.} and T. Ivers and H. Kuroda and D. McHerron and J. Pellerin and Y. Toyoshima and S. Subbanna and N. Kepler and L. Su",

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doi = "10.1109/.2005.1469238",

language = "English (US)",

isbn = "4900784001",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "126--127",

booktitle = "2005 Symposium on VLSI Technology, Digest of Technical Papers",

note = "2005 Symposium on VLSI Technology ; Conference date: 14-06-2005 Through 14-06-2005",

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AU - Leobandung, E.

AU - Nayakama, H.

AU - Mocuta, D.

AU - Miyamoto, K.

AU - Angyal, M.

AU - Meer, H. V.

AU - McStay, K.

AU - Ahsan, I.

AU - Allen, S.

AU - Azuma, A.

AU - Belyansky, M.

AU - Bentum, R. V.

AU - Cheng, J.

AU - Chidambarrao, D.

AU - Dirahoui, B.

AU - Fukasawa, M.

AU - Gerhardt, M.

AU - Gribelyuk, M.

AU - Halle, S.

AU - Harifuchi, H.

AU - Harmon, D.

AU - Heaps-Nelson, J.

AU - Hichri, H.

AU - Ida, K.

AU - Inohara, M.

AU - Inoue, K.

AU - Jenkins, K.

AU - Kawamura, T.

AU - Kim, B.

AU - Ku, S. K.

AU - Kumar, M.

AU - Lane, S.

AU - Liebmann, L.

AU - Logan, R.

AU - Melville, I.

AU - Miyashita, K.

AU - Mocuta, A.

AU - O'Neil, P.

AU - Ng, M. F.

AU - Nogami, T.

AU - Nomura, A.

AU - Norris, C.

AU - Nowak, E.

AU - Ono, M.

AU - Panda, S.

AU - Penny, C.

AU - Radens, C.

AU - Ramachandran, R.

AU - Ray, A.

AU - Rhee, S. H.

AU - Ryan, D.

AU - Shinohara, T.

AU - Sudo, G.

AU - Sugaya, F.

AU - Strane, J.

AU - Tan, Y.

AU - Tsou, L.

AU - Wang, L.

AU - Wirbeleit, F.

AU - Wu, S.

AU - Yamashita, T.

AU - Yan, H.

AU - Ye, Q.

AU - Yoneyama, D.

AU - Zamdmer, N.

AU - Zhong, H.

AU - Zhu, H.

AU - Zhu, W.

AU - Agnello, P.

AU - Bukofsky, S.

AU - Bronner, G.

AU - Crabbé, E.

AU - Freeman, G.

AU - Huang, S. F.

AU - Ivers, T.

AU - Kuroda, H.

AU - McHerron, D.

AU - Pellerin, J.

AU - Toyoshima, Y.

AU - Subbanna, S.

AU - Kepler, N.

AU - Su, L.

PY - 2005

Y1 - 2005

N2 - A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm 2 SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

AB - A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm 2 SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

UR - http://www.scopus.com/inward/record.url?scp=33745148992&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33745148992&partnerID=8YFLogxK

U2 - 10.1109/.2005.1469238

DO - 10.1109/.2005.1469238

M3 - Conference contribution

AN - SCOPUS:33745148992

SN - 4900784001

SN - 9784900784000

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 126

EP - 127

BT - 2005 Symposium on VLSI Technology, Digest of Technical Papers

T2 - 2005 Symposium on VLSI Technology

Y2 - 14 June 2005 through 14 June 2005

ER -

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

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