High-level synthesis with behavioral level multi-cycle path analysis

Keyphrases

• Behavioral Level 100%
• Path Analysis 100%
• High-level Synthesis 100%
• Multi-cycle Path 100%
• Logic Synthesis 80%
• Register Transfer Level 60%
• Resource Allocation 20%
• Latency 20%
• Level Description 20%
• High-level Synthesis Tools 20%
• Execution Time 20%
• Guard 20%
• Control Flow 20%
• Clock Frequency 20%
• Resource Binding 20%
• Allocation Scheduling 20%
• Resource Scheduling 20%
• FPGA Architecture 20%
• Logic Level 20%
• Design Quality 20%
• All-Path 20%
• Hardware Description 20%
• Time-area 20%
• Product Improvement 20%
• Multi-cycle Optimization 20%
• Area Product 20%
• LegUp 20%

Computer Science

• High Level Synthesis 100%
• Logic Synthesis 100%
• Register-Transfer Level 75%
• And-States 25%
• Resource Allocation 25%
• Synthesis Tool 25%
• Level Description 25%
• Execution Time 25%
• Control Flow 25%
• Clock Cycle 25%
• Logic Level 25%