High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

Keith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this study, we propose a low-cost approach to error detection for arithmetic orientated data paths by performing lightweight shadow computations in modulo-3 space for each main computation. By leveraging the binding and scheduling flexibility of high-level synthesis, we detect errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We evaluated our technique with 12 high-level synthesis benchmarks using FPGA emulated netlist-level error injection. We observe coverages of 99.13% for stuck-at faults, 99.46% for soft errors, and 99.67% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging error detection latencies on the order of 10 cycles (3 orders of magnitude faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175x increase in reliability against soft errors.

Original languageEnglish (US)
Title of host publication2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450335201
StatePublished - Jul 24 2015
Event52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States
Duration: Jun 7 2015Jun 11 2015

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
Country/TerritoryUnited States
CitySan Francisco


  • High-level synthesis
  • aliasing
  • automation
  • binding
  • checkpointing
  • datapath
  • electrical faults
  • error detection
  • high performance
  • logic optimization
  • low cost
  • modulo arithmetic
  • optimization
  • pIPelining
  • rollback recovery
  • scheduling
  • shadow logic
  • soft errors
  • state machine
  • stuck-at faults
  • timing errors

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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