TY - JOUR
T1 - High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer with Single FPGA
AU - Kou, Zhengchang
AU - You, Qi
AU - Kim, Jihun
AU - Dong, Zhijie
AU - Lowerison, Matthew R.
AU - Sekaran, Nathiya Vaithiyalingam Chandra
AU - Llano, Daniel Adolfo
AU - Song, Pengfei
AU - Oelze, Michael L.
N1 - Funding Information:
The work of Zhengchang Kou was supported by a Beckman Institute Graduate Fellowship. The work of Matthew R. Lowerison and Nathiya Vaithiyalingam Chandra Sekaran was supported by Beckman Institute Postdoctoral Fellowships. This work was supported in part by the National Institutes of Health under Grants R21EB024133, R21EB023403, R21EB030743, R01CA251939, R21EB030072, R01EB031040, and R21AG077173, and in part by the National Science Foundation under Award 2237166.
Publisher Copyright:
© 2007-2012 IEEE.
PY - 2023/6/1
Y1 - 2023/6/1
N2 - Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability th at allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify th at the image quality was not compromised for speed.
AB - Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability th at allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify th at the image quality was not compromised for speed.
KW - Beamforming
KW - FPGA
KW - parallelization
KW - real-time
KW - super-resolution imaging
KW - ultrafast ultrasound
UR - http://www.scopus.com/inward/record.url?scp=85153499454&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85153499454&partnerID=8YFLogxK
U2 - 10.1109/TBCAS.2023.3267614
DO - 10.1109/TBCAS.2023.3267614
M3 - Article
C2 - 37067960
AN - SCOPUS:85153499454
SN - 1932-4545
VL - 17
SP - 446
EP - 457
JO - IEEE Transactions on Biomedical Circuits and Systems
JF - IEEE Transactions on Biomedical Circuits and Systems
IS - 3
ER -