High-Level Synthesis-Based Approach for Accelerating Scientific Codes on FPGAs

Ramshankar Venkatakrishnan, Ashish Misra, Volodymyr Kindratenko

Research output: Contribution to journalArticlepeer-review


Traditionally, Hardware Description Languages (HDLs), such as Verilog or VHDL, have been used for programming Field-Programmable Gate Arrays (FPGAs). However, this approach requires an advanced knowledge of digital design and computer architecture. Recently emerged high-level design tools make it easier for the programmers to code complex designs in C/Cþþ. High-level synthesis (HLS)1 and OpenCL2 are the two leading high-level design platforms that are becoming widely used for programming FPGAs. Their proponents claim that these tools require little to no knowledge of the hardware design principles and can significantly improve developer's productivity. In this article, we explore these two high-level design approaches from the point of view of a software developer. We use Xilinx Vivado HLS C/Cþþ ver. 2019.13 and Xilinx SDAccel OpenCL ver. 2019.14 to implement a cross-correlation operation from scratch and synthesize it for a Xilinx u250 Alveo FPGA board.5 The selected operation is at the core of convolutional neural networks and is generally nontrivial to implement using a traditional HDL methodology, but is rather simple to implement using a programming language, such as C. We opted not to focus on the design optimization, but rather getting a design that works on the FPGA with the minimal time spent on its implementation. We use the Xilinx SDAccel platform that provides support for implementing both OpenCL-and HLSbased kernels to run on an FPGA using OpenCL drivers on the host platform. We also took note of how capable each tool is in terms of optimization, without using tool-specific attributes or pragmas, as well as how well it utilizes the available hardware. We find that HLS tools are easy to learn and the time to design is much shorter compared to the HDL approach. However, a good knowledge of digital design and the underlying FPGA architecture is still needed to deliver a high-performance implementation.

Original languageEnglish (US)
Article number9121601
Pages (from-to)104-109
Number of pages6
JournalComputing in Science and Engineering
Issue number4
StatePublished - Jul 1 2020

ASJC Scopus subject areas

  • General Computer Science
  • General Engineering


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