High-level power estimation and low-power design space exploration for FPGAs

Keyphrases

• Resource Allocation 100%
• Low Power 100%
• Resource Binding 100%
• Power Estimation 100%
• Power Estimator 100%
• Low-power Design 100%
• Design Space Exploration 100%
• Power Play 66%
• Estimation Accuracy 33%
• Logic Element 33%
• Gate Level 33%
• Design Space 33%
• Multiplexer 33%
• Traditional Resources 33%
• Power Reduction 33%
• FPGA Architecture 33%
• Quartus II 33%
• Altera 33%
• Power Minimization 33%
• DSP Core 33%

Computer Science

• Resource Allocation 100%
• Low-Power Design 100%
• Design-Space Exploration 100%
• Experimental Result 33%
• Estimation Accuracy 33%
• Multiplexer 33%
• Pay Special Attention 33%
• Logic Element 33%

Engineering

• Field Programmable Gate Arrays 100%
• Design Space 100%
• Power Estimation 100%
• Power Level 50%
• Tasks 25%
• Experimental Result 25%
• Special Attention 25%
• Multiplexer 25%