High-level power estimation and low-power design space exploration for FPGAs

Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a simultaneous resource allocation and binding algorithm for FPGA power minimization. To fully validate our methodology and result, our work targets a real FPGA architecture - Altera Stratix FPGA [2], which includes generic logic elements, DSP cores, and memories, etc. We design a highlevel power estimator for this architecture and evaluate its estimation accuracy against a commercial gate-level power estimator - Quartus II PowerPlay Analyzer [1]. During the synthesis stage, we pay special attention to interconnections and multiplexers. We concentrate on resource allocation and binding tasks because they are the key steps to determine the interconnections. We use a novel approach to explore the design space. Experimental results show that our high-level power estimator is 8.7% away from PowerPlay Analyzer. Meanwhile, we are able to achieve a significant amount of power reduction (32%) with better circuit speed (16%) compared to a traditional resource allocation and binding algorithm.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages529-534
Number of pages6
DOIs
StatePublished - 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Country/TerritoryJapan
CityYokohama
Period1/23/071/27/07

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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