TY - GEN
T1 - High-level power estimation and low-power design space exploration for FPGAs
AU - Chen, Deming
AU - Cong, Jason
AU - Fan, Yiping
AU - Zhang, Zhiru
PY - 2007
Y1 - 2007
N2 - In this paper, we present a simultaneous resource allocation and binding algorithm for FPGA power minimization. To fully validate our methodology and result, our work targets a real FPGA architecture - Altera Stratix FPGA [2], which includes generic logic elements, DSP cores, and memories, etc. We design a highlevel power estimator for this architecture and evaluate its estimation accuracy against a commercial gate-level power estimator - Quartus II PowerPlay Analyzer [1]. During the synthesis stage, we pay special attention to interconnections and multiplexers. We concentrate on resource allocation and binding tasks because they are the key steps to determine the interconnections. We use a novel approach to explore the design space. Experimental results show that our high-level power estimator is 8.7% away from PowerPlay Analyzer. Meanwhile, we are able to achieve a significant amount of power reduction (32%) with better circuit speed (16%) compared to a traditional resource allocation and binding algorithm.
AB - In this paper, we present a simultaneous resource allocation and binding algorithm for FPGA power minimization. To fully validate our methodology and result, our work targets a real FPGA architecture - Altera Stratix FPGA [2], which includes generic logic elements, DSP cores, and memories, etc. We design a highlevel power estimator for this architecture and evaluate its estimation accuracy against a commercial gate-level power estimator - Quartus II PowerPlay Analyzer [1]. During the synthesis stage, we pay special attention to interconnections and multiplexers. We concentrate on resource allocation and binding tasks because they are the key steps to determine the interconnections. We use a novel approach to explore the design space. Experimental results show that our high-level power estimator is 8.7% away from PowerPlay Analyzer. Meanwhile, we are able to achieve a significant amount of power reduction (32%) with better circuit speed (16%) compared to a traditional resource allocation and binding algorithm.
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U2 - 10.1109/ASPDAC.2007.358040
DO - 10.1109/ASPDAC.2007.358040
M3 - Conference contribution
AN - SCOPUS:44949258060
SN - 1424406293
SN - 9781424406296
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 529
EP - 534
BT - Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Y2 - 23 January 2007 through 27 January 2007
ER -