Hierarchical decomposition methodology for single-stage clock circuits

Gary Ellis, Lawrence T. Pileggi, Robin A Rutenbar

Research output: Contribution to journalConference articlepeer-review


This paper describes a methodology for designing the interconnect distribution for single-stage clock circuits using a hierarchical decomposition. This new method of splitting the design into global and local distributions improves the optimization efficiency and enhances both wireability and performance. A novel use of the Delaunay triangulation provides a means for efficiently constructing and optimizing the local distribution. The combination of these global and local solutions produces layouts with less wirelength and an average 3X performance improvement over flat solutions while keeping the worst case skew below 50ps. When these designs are wiresized, they achieve a 25% reduction in wire area over their flat circuit counterparts due to the reduction in downstream capacitive wire loading.

Original languageEnglish (US)
Pages (from-to)115-118
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 1997
EventProceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: May 5 1997May 8 1997

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Hierarchical decomposition methodology for single-stage clock circuits'. Together they form a unique fingerprint.

Cite this